參數(shù)資料
型號： MB90F949APF
元件分類： 微控制器/微處理器
英文描述： MICROCONTROLLER, PQFP100
封裝： 14 X 20 MM, 3.35 MM HEIGHT, 0.65 MM PITCH, PLASTIC, QFP-100
文件頁數(shù)： 33/57頁
文件大?。?/td> 1586K
代理商： MB90F949APF
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7544 Group
MITSUBISHI MICROCOMPUTERS
39
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Som
e parametric
limits
are
subject
to change.
NOTES ON PERIPHERAL FUNCTIONS
s Interrupt
When setting the followings, the interrupt request bit may be set to
“1”.
When setting external interrupt active edge
Related register: Interrupt edge selection register (address
003A16)
Timer X mode register (address 2B16)
Timer A mode register (address 1D16)
When not requiring the interrupt occurrence synchronized with
these setting, take the following sequence.
Set the corresponding interrupt enable bit to “0” (disabled).
Set the interrupt edge select bit (active edge switch bit) to “1”.
Set the corresponding interrupt request bit to “0” after 1 or
more instructions have been executed.
Set the corresponding interrupt enable bit to “1” (enabled).
s Timers
When n (0 to 255) is written to a timer latch, the frequency divi-
sion ratio is 1/(n+1).
When a count source of timer X, timer Y or timer Z is switched,
stop a count of timer X.
s Timer A
CNTR1 interrupt active edge selection
CNTR1 interrupt active edge depends on the CNTR1 active edge
switch bit.
When this bit is “0”, the CNTR1 interrupt request bit is set to “1” at
the falling edge of the CNTR1 pin input signal. When this bit is “1”,
the CNTR1 interrupt request bit is set to “1” at the rising edge of
the CNTR1 pin input signal.
However, in the pulse width HL continuously measurement mode,
CNTR1 interrupt request is generated at both rising and falling
edges of CNTR1 pin input signal regardless of the setting of
CNTR1 active edge switch bit.
s Timer X
CNTR0 interrupt active edge selection
CNTR0 interrupt active edge depends on the CNTR0 active edge
switch bit.
When this bit is “0”, the CNTR0 interrupt request bit is set to “1” at
the falling edge of CNTR0 pin input signal. When this bit is “1”, the
CNTR0 interrupt request bit is set to “1” at the rising edge of
CNTR0 pin input signal.
s Serial I/O
Serial I/O interrupt
When setting the transmit enable bit to “1”, the serial I/O transmit
interrupt request bit is automatically set to “1”. When not requiring
the interrupt occurrence synchronized with the transmission en-
abled, take the following sequence.
Set the serial I/O transmit interrupt enable bit to “0” (disabled).
Set the transmit enable bit to “1”.
Set the serial I/O transmit interrupt request bit to “0” after 1 or
more instructions have been executed.
Set the serial I/O transmit interrupt enable bit to “1” (enabled).
I/O pin function when serial I/O is enabled.
The functions of P12 and P13 are switched with the setting values
of a serial I/O mode selection bit and a serial I/O synchronous
clock selection bit as follows.
(1) Serial I/O mode selection bit
→ “1” :
Clock synchronous type serial I/O is selected.
Setup of a serial I/O synchronous clock selection bit
“0” : P12 pin turns into an output pin of a synchronous clock.
“1” : P12 pin turns into an input pin of a synchronous clock.
Setup of a SRDY1 output enable bit (SRDY)
“0” : P13 pin can be used as a normal I/O pin.
“1” : P13 pin turns into a SRDY output pin.
(2) Serial I/O mode selection bit
→ “0” :
Clock asynchronous (UART) type serial I/O is selected.
Setup of a serial I/O synchronous clock selection bit
“0”: P12 pin can be used as a normal I/O pin.
“1”: P12 pin turns into an input pin of an external clock.
When clock asynchronous (UART) type serial I/O is selected, it is
P13 pin. It can be used as a normal I/O pin.
s A-D Converter
The comparator uses internal capacitors whose charge will be lost
if the clock frequency is too low.
Make sure that f(XIN) is 500kHz or more during A-D conversion.
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