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參數(shù)資料
| 型號： | MB90F949PF |
| 廠商： | FUJITSU LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, 24 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁數(shù)： | 31/65頁 |
| 文件大?。?/td> | 713K |
| 代理商： | MB90F949PF |
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MB90945 Series
37
(Continued)
: The interrupt request flag is cleared by the EI2OS interrupt clear signal.
: The interrupt request flag is cleared by the EI2OS interrupt clear signal. A stop request is available.
: Unavailable
N/A : The interrupt request flag is not cleared by the EI2OS interrupt clear signal.
Notes :
For a peripheral module with two interrupt causes for a single interrupt number, both interrupt request
flags are cleared by the EI2OS interrupt clear signal.
At the end of EI2OS, the EI2OS clear signal will be asserted for all the interrupt flags assigned to the same
interrupt number. If one interrupt flag starts the EI2OS and in the meantime another interrupt flag is set
by hardware event, the later event is lost because the flag is cleared by the EI2OS clear signal caused
by the first event. So it is recommended not to use the EI2OS for this interrupt number.
If EI2OS is enabled, EI2OS is initiated when one of the two interrupt signals in the same interrupt control
register (ICR) is asserted. This means that different interrupt sources share the same EI2OS Descriptor
which should be unique for each interrupt source. For this reason, when one interrupt source uses the
EI2OS, the other interrupt should be disabled.
Interrupt cause
EI2OS
clear
Interrupt vector
Interrupt control
register
Number
Address
Number
Address
UART 2 RX / UART 3 RX
#39
FFFF60H
ICR14
0000BEH
UART 2 TX / UART 3 TX
#40
FFFF5CH
Flash memory
N/A
#41
FFFF58H
ICR15
0000BFH
Delayed interrupt
N/A
#42
FFFF54H
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