參數(shù)資料
型號： MB90F967SPMT
廠商： FUJITSU LTD
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 24 MHz, MICROCONTROLLER, PQFP48
封裝： 7 X 7 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LQFP-48
文件頁數(shù)： 18/60頁
文件大?。?/td> 1876K
代理商： MB90F967SPMT
MB90960 Series
DS07-13749-2E
25
(Continued)
Address
Register
Abbreviation
Access
Resource name
Initial value
000050H Input Capture Control Status 0/1
ICS01
R/W
Input Capture 0/1
00000000B
000051H Input Capture Edge 0/1
ICE01
R/W, R
XXX0X0XXB
000052H Input Capture Control Status 2/3
ICS23
R/W
Input Capture 2/3
00000000B
000053H Input Capture Edge 2/3
ICE23
R
XXXXXXXXB
000054H
to
000063H
Reserved
000064H Timer Control Status 2
TMCSR2
R/W
16-bit Reload Timer 2
00000000B
000065H Timer Control Status 2
TMCSR2
R/W
XXXX0000B
000066H Timer Control Status 3
TMCSR3
R/W
16-bit Reload Timer 3
00000000B
000067H Timer Control Status 3
TMCSR3
R/W
XXXX0000B
000068H A/D Control Status 0
ADCS0
R/W
A/D Converter
000XXXX0B
000069H A/D Control Status 1
ADCS1
R/W, W
0000000XB
00006AH A/D Data Register 0
ADCR0
R
00000000B
00006BH A/D Data Register 1
ADCR1
R
XXXXXX00B
00006CH A/D Converter Setting 0
ADSR0
R/W
00000000B
00006DH A/D Converter Setting 1
ADSR1
R/W
00000000B
00006EH
Reserved
00006FH ROM Mirror Function Select
ROMM
W
ROM Mirror
XXXXXXX1B
000070H
to
00009DH
Reserved
00009EH Address Detect Control Register 0
PACSR0
R/W
Address Match
Detection 0
00000000B
00009FH Delayed Interrupt/Release Register
DIRR
R/W
Delayed Interrupt
generation module
XXXXXXX0B
0000A0H
Low-power Consumption Mode
Control Register
LPMCR
W, R/W
Low-Power
consumption
Control Circuit
00011000B
0000A1H Clock Selection Register
CKSCR
R, R/W
Low-Power
consumption
Control Circuit
11111100B
0000A2H
to
0000A7H
Reserved
0000A8H Watchdog Timer Control Register
WDTC
R, W
Watchdog Timer
XXXXX111B
0000A9H Time-base Timer Control Register
TBTC
W, R/W
Time-base Timer
1XX00100B
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