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參數(shù)資料
| 型號(hào)： | MB90V590ACR |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, 16 MHz, MICROCONTROLLER, CPGA256 |
| 封裝： | CERAMIC, PGA-256 |
| 文件頁(yè)數(shù)： | 29/52頁(yè) |
| 文件大?。?/td> | 718K |
| 代理商： | MB90V590ACR |
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MB90590/590G Series
35
*1: The interrupt request flag is cleared by the I2OS interrupt clear signal.
*2: The interrupt request flag is cleared by the I2OS interrupt clear signal. A stop request is available.
N/A:The interrupt request flag is not cleared by the I2OS interrupt clear signal.
Note:
For a peripheral module with two interrupt for a single interrupt number, both interrupt request flags are
cleared by the I2OS interrupt clear signal.
At the end of I2OS, the I2OS clear signal will be asserted for all the interrupt flags assigned to the same in-
terrupt number. If one interrupt flag starts the I2OS and in the meantime another interrupt flag is set by a
hardware event, the later event is lost because the flag is cleared by the I2OS clear signal caused by the
first event. So it is recommended not to use the I2OS for this interrupt number.
If I2OS is enabled, I2OS is initiated when one of the two interrupt signals in the same interrupt control register
(ICR) is asserted. This means that different interrupt sources share the same I2OS Descriptor which should
be unique for each interrupt source. For this reason, when one interrupt source uses the I2OS, the other
interrupt should be disabled.
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