
41
MB90220 Series
4. UART1
The UART1 is a serial I/O port for asynchronous communications (start-stop synchronization) or CLK
synchronized communications. It has the following features:
Full-duplex double buffering
Permits asynchronous (start-stop synchronization) and CLK synchronous communications
Multiprocessor mode support
Built-in dedicated baud rate generator
Asynchronous:
9615, 31250, 4808, 2404, and 1202 bps
CLK synchronization: 1 M, 500 K, 250 K bps
Arbitray baud-rate setting from external clock input or internal timer
Error detection function (parity errors, framing errors, and overrun errors)
Transfer in format NRZ
Extended supports intelligent I/O service
(1) Register Configuration
bit15
PEN
bit14
P
bit13
SBL
bit12
CL
bit11
A/D
bit10
REC
bit9
RXE
TXE
bit8
00002F
H
SCR
00000100
B
bit7
MD1
bit6
MD0
bit5
CS2
bit4
CS1
bit3
CS0
bit2
BCH
bit1
SCKE
SOE
bit0
00002E
H
SMR
00000000
B
D7
(R)
D6
(R)
D5
(R)
D4
(R)
D3
(R)
D2
(R)
D1
(R)
D0
(R)
000030
H
SIDR
XXXXXXXX
B
D7
D6
D5
D4
D3
D2
D1
D0
000030
H
SODR
XXXXXXXX
B
PE
ORE
FRE
RDRF
TDRE
—
RIE
TIE
000031
H
SSR
00001-00
B
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Register name Address
Register name Address
Register name Address
Register name Address
Register name Address
Initial value
Initial value
Initial value
Initial value
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R)
(R/W)
(R/W)
(W)
(W)
(W)
(W)
(W)
(W)
(W)
(W)
(R)
(R)
(R)
(R)
(R)
(R/W)
(R/W)
Mode Register (SMR)
SCR (Control Register)
Input Data Register (SIDR)/Serial Output Data Register (SODR)
SSR (Status Register)