![](http://datasheet.mmic.net.cn/330000/MB90P234_datasheet_16438148/MB90P234_25.png)
25
MB90230 Series
I
INTERRUPT VECTORS AND INTERRUPT CONTROL REGISTERS FOR INTERRUPT
SOURCES
: The request flag is cleared by the EI
2
OS interrupt clear signal.
: The request flag is cleared by the EI
2
OS interrupt clear signal. The stop request is available.
: The request flag is not cleared by the EI
2
OS interrupt clear signal.
Interrupt source
I
2
OS
support
Interrupt vector
Interrupt control
register
No.
Address
ICR
Address
Reset
×
×
×
#08
08
H
FFFFDC
H
—
—
INT9 instruction
#09
09
H
FFFFD8
H
—
—
Exceptional
#10
0A
H
FFFFD4
H
—
—
External interrupt (INT0) 0 ch
#11
0B
H
FFFFD0
H
ICR00
0000B0
H
External interrupt (INT1) 1 ch
#12
0C
H
FFFFCC
H
External interrupt (INT2) 2 ch
#13
0D
H
FFFFC8
H
ICR01
0000B1
H
External interrupt (INT3) 3 ch
#14
0E
H
FFFFC4
H
Extended serial I/O interface
#15
0F
H
FFFFC0
H
ICR02
0000B2
H
Serial E
2
PROM interface
#17
11
H
FFFFB8
H
ICR03
0000B3
H
Input capture channel 0
#19
13
H
FFFFB0
H
ICR04
0000B4
H
Input capture channel 1
#21
15
H
FFFFA8
H
ICR05
0000B5
H
Input capture channel 2
#23
17
H
FFFFA0
H
ICR06
0000B6
H
Input capture channel 3
#24
18
H
FFFF9C
H
Output compare channel 0
#25
19
H
FFFF98
H
ICR07
0000B7
H
Output compare channel 1
#26
1A
H
FFFF94
H
Output compare channel 2
#27
1B
H
FFFF90
H
ICR08
0000B8
H
Output compare channel 3
#28
1C
H
FFFF8C
H
Output compare channel 4
#29
1D
H
FFFF88
H
ICR09
0000B9
H
Output compare channel 5
#30
1E
H
FFFF84
H
16-bit free run timer overflow
#31
1F
H
FFFF80
H
ICR10
0000BA
H
Timebase timer overflow
#32
20
H
FFFF7C
H
8-bit PPG timer
#33
21
H
FFFF78
H
ICR11
0000BB
H
Level comparator
#34
22
H
FFFF74
H
UART reception
#35
23
H
FFFF70
H
ICR12
0000BC
H
UART transmission
#37
25
H
FFFF68
H
ICR13
0000BD
H
End of A/D conversion
#39
27
H
FFFF60
H
ICR14
0000BE
H
Delayed interrupt
×
×
#42
2A
H
FFFF54
H
ICR15
0000BF
H
Stack fault
#256
FF
H
FFFC00
H
—
—