參數(shù)資料
型號: MB91233LLGA-G-xxx-BNDE1
廠商: FUJITSU LTD
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 33.6 MHz, RISC MICROCONTROLLER, PQFP120
封裝: CERAMIC, LQFP-120
文件頁數(shù): 5/68頁
文件大小: 1635K
代理商: MB91233LLGA-G-XXX-BNDE1
MB91230 Series
DS07–16506–3E
13
(Continued)
Pin no.
Pin name
I/O circuit
type
Description
LQFP
FLGA
79 to 82
F10, E11, E9,
D11
SEG28 to
SEG31
J
LCD controller/driver LCD segment output pins.
This function is valid when corresponding bit of PFR6
register is set to peripheral function.
P64 to P67
General purpose input/output ports. (open-drain)
This function is valid when corresponding bit of PFR6
register is set to port function.
83 to 86
E10, D12,
C11, D10
COM0 to
COM3
I
LCD controller/driver common output pins.
This function is valid when corresponding bit of PFR7
register is set to peripheral function.
P70 to P73
General purpose input/output ports.
This function is valid when corresponding bit of PFR7
register is set to port function.
87 to 89
C12, B11, D9
MD2,
MD1,
MD0
H
Mode input pins.
90
B12
INIT
G
External reset input.
91 to 94
A12, B10,
C10, A11
V0 to V3
LCD controller/driver reference power supply input
pins.
95
D8
SIN0
D
UART0 data input.
When using this function, corresponding bit of DDR0
register is set to input.
P00
General purpose input/output port.
This function is always valid.
96
B9
SOT0
D
UART0 data output.
This function is valid when corresponding bit of PFR0
register is set to peripheral function.
P01
General purpose input/output port.
This function is valid when corresponding bit of PFR0
register is set to port function.
97
A10
SCK0
D
UART0 clock input/output.
This function is valid when corresponding bit of PFR0
register is set to peripheral function.
P02
General purpose input/output port.
This function is valid when corresponding bit of PFR0
register is set to port function.
98
C9
SIN1
D
UART1 data input.
This function is valid when corresponding bit of DDR0
register is set to input.
P03
General purpose input/output port.
This function is always valid.
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