參數(shù)資料
型號(hào)： MB91233LPMC1-G-XXXE1
廠商： FUJITSU LTD
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 33.6 MHz, RISC MICROCONTROLLER, PQFP120
封裝： PLASTIC, LQFP-120
文件頁(yè)數(shù)： 18/68頁(yè)
文件大?。?/td> 1635K
代理商： MB91233LPMC1-G-XXXE1
MB91230 Series
DS07–16506–3E
25
■ MODE SETTINGS
The FR family uses mode pins (MD2 to MD0) and a mode data to set the operation mode.
Mode Pins
The MD2 to MD0 pins specify how the mode vector fetch and reset vector fetch is performed.
Setting is prohibited other than that shown in the following table.
Mode data
Data written to the internal mode register (MODR) by a mode vector fetch is called mode data.
After an operation mode has been set in the mode register, the device operates in the operation mode.
The mode data is set by all reset source. User programs cannot set data to the mode register.
Details of mode data description
Bit31 to bit24 are all reserved bits.
Be sure to set this bit to “00000111”.
Operation is not guaranteed when any value other than “00000111” is set.
Note : Mode data set in the mode vector must be placed as byte data at 000FFFF8H.
Use the highest byte from bit31 to bit24 for placement as the FR family uses the big endian for byte
endian.
Mode Pins
Mode name
Reset vector
access area
Remarks
MD2
MD1
MD0
0
Internal ROM mode vector
Internal
0
1
External ROM mode vector
External
Not supported by this model.
31
bit
30
29
28
27
26
25
24
00
01
11
Operation mode setting bits
31
bit
24 23
16 15
8 7
0
XXXXXXXX
000FFFF8H
000FFFFCH
XXXXXXXX
Mode Data
Reset Vector
XXXXXXXX
Incorrect
Correct
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