參數(shù)資料
型號: MB91302APFF-G-001-BNDE1
元件分類: 微控制器/微處理器
英文描述: 32-BIT, MROM, 68 MHz, RISC MICROCONTROLLER, PQFP144
封裝: 0.40 MM PITCH, PLASTIC, LQFP-144
文件頁數(shù): 62/140頁
文件大小: 2841K
代理商: MB91302APFF-G-001-BNDE1
MB91301 Series
28
DS07-16502-4E
Configuration batch file
The example batch file below sets the mode vector and sets up the CS0 configuration register for the download
area. Use values appropriate to the hardware in the wait, timing, and other settings.
#---------------------------------------------------------
# Set MODR (0x7fd) =Enable In memory+16 bit External Bus
set mem/byte 0x7fd=0x5
#---------------------------------------------------------
# Set ASR0 (0x640) ; 0x0010_0000 - 0x002f_ffff
set mem/halfword 0x640=0x0010
#---------------------------------------------------------
# Set ACR0 (0x642)
#
; ASZ [3:0]=0101:2 Mbytes
#
; DBW [1:0]=01:16 bit width, automatically set from
MODR
#
; BST [1:0]=00:1 burst (16 bit x 2)
#
; SREN=0:Disable BRQ
#
; PFEN=1:Enable Pre fetch buffer
#
; WREN=1:Enable Write operation
#
; LEND=0: Big endian
#
; TYPE [3:0]=0010:WEX: Disable RDY
set mem/harfword 0x642=0x5462
#---------------------------------------------------------
# Set AWR0 (0x660)
#
; W15-12=0010:auto wait=2
#
; WR07, 06=01:RD, WR delay=1cycle
#
; W05, 04=01:WR->WR delay=1cycle (for WEX)
#
; W03 =1:MCLK->RD/WR delay=0.5cycle
#
;
:for async Memory
#
; W02 =0:ADR->CS delay=0
#
; W01 =0:ADR->RD/WR setup 0cycle
#
; W00 =RD/WR->ADR hold 0cycle
set mem/halfword 0x660=0x2058
#---------------------------------------------------------
Emulation memory
If SRAM as the emulation memory is built on target board, SRAM for be accessed by RD, WR signal, and
+BYTE
control signal can not be used. (The external bus is initialized to the bus mode for accessing RD, WRn after reset.)
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