參數(shù)資料
型號(hào): MB91302APFF-G-010-BNDE1
廠商: FUJITSU LTD
元件分類: 微控制器/微處理器
英文描述: 32-BIT, MROM, 68 MHz, RISC MICROCONTROLLER, PQFP144
封裝: 0.40 MM PITCH, PLASTIC, LQFP-144
文件頁數(shù): 62/96頁
文件大?。?/td> 2641K
代理商: MB91302APFF-G-010-BNDE1
MB90520B Series
DS07-13707-5E
73
20. Low Power Consumption (Standby) Modes
The power consumption of F2MC-16LX devices can be reduced by various settings relating to the operating
clock selection.
Functions of each CPU operation mode
CPU Operation
Clock
Operation
Mode
Explanation
PLL clock
Normal run
The CPU and peripheral functions operate using the oscillation clock (HCLK) mul-
tiplied by the PLL circuit.
Sleep
The peripheral functions only operate using the oscillation clock (HCLK) multiplied
by the PLL circuit.
Pseudo-
clock
The timebase timer only operates using the oscillation clock (HCLK) multiplied by
the PLL circuit.
Stop
The oscillation clock is stopped and the CPU and peripherals halt operation.
Main clock
Normal run
The CPU and peripheral functions operate using the oscillation clock (HCLK) di-
vided by 2.
Sleep
The peripheral functions only operate using the oscillation clock (HCLK) divided
by 2.
Stop
The oscillation clock is stopped and the CPU and peripherals halt operation.
Sub-clock
Normal run
The CPU and peripheral functions operate using the sub-clock (SCLK) . The os-
cillation clock stops.
Sleep
The peripheral functions only operate using the sub-clock (SCLK) . The oscillation
clock stops.
Clock
The clock timer only operates using the sub-clock (SCLK) . The oscillation clock
stops.
Stop
The oscillation clock and sub-clock are stopped and the CPU and peripherals halt
operation.
CPU
intermittent
operation
Normal run
The oscillation clock (HCLK) divided by 2 operates intermittently for fixed time in-
tervals.
Hardware
standby
Stop
The oscillation clock and sub-clock are stopped and the CPU and peripherals halt
operation.
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