參數(shù)資料
型號(hào): MB91302APFF-G-020-BNDE1
元件分類: 微控制器/微處理器
英文描述: 32-BIT, MROM, 68 MHz, RISC MICROCONTROLLER, PQFP144
封裝: 0.40 MM PITCH, PLASTIC, LQFP-144
文件頁數(shù): 22/140頁
文件大?。?/td> 2841K
代理商: MB91302APFF-G-020-BNDE1
MB91301 Series
118
DS07-16502-4E
At slave mode operation
(AVCC
= VCC = 3.3 ± 0.3 V, AVSS = VSS = 0.0 V, Ta = 0 °C to +70 °C)
*1 : M
= resource clock cycle (ns)
*2 : A high-speed mode I2C bus device can be used for a standard mode I2C bus system as long as the device
satisfies a requirement of “tSUDAT
≥ 250 ns”.
When a certain device does not extend the “L” period of the SCL signal, the next data must be output to the
SDA line within 1250 ns (maximum SDA/SCL rise time
+ tSUDATA) in which the SCL line is released.
*3 : For use at over 100 kHz, set the resource clock frequency to at least 6 MHz.
*4 : R and C represent the pull-up resistor and load capacitor of the SCL and SDA output lines.
Parameter
Sym-
bol
Pin
Conditions
Typical mode
Fast mode*3
Unit
Remarks
Min
Max
Min
Max
SCL clock frequency
fSCL
SCL0, SCL1
R
= 1 k,
C
= 50 pF*4
0
100
0
400
kHz
“L” period of SCL clock tLOW
SCL0, SCL1
4.7
1.3
s
“H” period of SCL clock tHIGH
SCL0, SCL1
4.0
0.6
s
BUS free time between
“STOP condition” and
“START condition”
tBUS
SDA0, SDA1
4.7
1.3
s
SCL
↓→SDA output
delay time
tHDDAT
SCL0, SCL1,
SDA0, SDA1
5
× M*1
5
× M*1 ns
Setup time of “repeat
START condition”
SCL
↑→SDA↓
tSUSTA
SCL0, SCL1,
SDA0, SDA1
4.7
0.6
s
Hold time of “repeat
START condition”
SDA
↓→SCL↓
tHDSTA
SCL0, SCL1,
SDA0, SDA1
4.0
0.6
s
After that, the
first clock pulse
is generated.
Setup time of “STOP
condition”
SCL
↑→SDA↑
tSUSTO
SCL0, SCL1,
SDA0, SDA1
4.0
0.6
s
SDA data input hold
time (vs. SCL
↓)
tHDDAT SDA0, SDA1
2
×
M*1
2
×
M*1
s
SDA data input setup
time (vs. SCL
↑)
tHDSTA SDA0, SDA1
250
100*2
ns
SDA
SCL
VOH
VOL
tLOW
VOL
tHIGH
tSUSTA
tHDSTA
VOH
tSUSTO
tBUS
tHDSTA
tHDDAT
fSCL
tSUDAT
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