參數(shù)資料
型號(hào): MB91314APMC-GE1
元件分類(lèi): 微控制器/微處理器
英文描述: 32-BIT, MROM, 33 MHz, RISC MICROCONTROLLER, PQFP120
封裝: 16 X 16 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LQFP-120
文件頁(yè)數(shù): 25/73頁(yè)
文件大?。?/td> 810K
代理商: MB91314APMC-GE1
MB91314A Series
31
■ MODE SETTINGS
The FR family sets the operation mode using mode pins (MD2, MD1, and MD0) and a mode register (MODR).
1.
Mode Pins
The MD2, MD1, and MD0 pins specify how the mode vector fetch is performed.
Note: Values other than those listed in the table are prohibited.
2.
Mode Register (MODR)
Detailed explanation of register
Data written to the mode register by mode vector fetch is referred to as mode data.
When the mode register is set, the operation mode set in this register is used for operation.
The mode register is set when any reset source occurs.
Mode data cannot be written by the user program.
Note : Conventionally, the address (000007FFH) of the mode register for the FR family holds nothing.
The register can be updated in emulator mode. In this case, please use the instruction of the data transfer for
the 8-bit length.
Any 16/32-bit length transfer instruction cannot be used to write data to the mode register.
Detailed explanation of mode data
[bit 7 to bit 2] Reserved bits
Be sure to set these bits to “000001B”.
Setting the bits to any value other than “000001B” may result in an unpredictable operation.
Mode Pins
Mode name
Reset vector access area
MD2
MD1
MD0
0
Internal ROM mode vector
Internal
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 0
XXXXXXXXB
0
WTH1
bit 1
0
1
WTH0
00
MODR
0007FDH
[Initial Value]
Operation mode setting bits
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 0
XXXXXXXXB
0
WTH1
bit 1
0
1
WTH0
00
Operation mode setting bits
[Initial Value]
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