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參數(shù)資料
| 型號： | MB91316APMC-G-XXXE1 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, MROM, 40.8 MHz, RISC MICROCONTROLLER, PQFP176 |
| 封裝： | 24 X 24 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LQFP-176 |
| 文件頁數(shù)： | 14/71頁 |
| 文件大?。?/td> | 575K |
| 代理商： | MB91316APMC-G-XXXE1 |
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MB91319R Series
21
Restrictions
Common in MB91319R series
(1) Clock control block
Take the oscillation stabilization wait time during Low level input to the INIT pin.
(2) Bit Search Module
The 0-detection data register (BSD0) , 1-detection data register (BSD1) , and transition-detection data
register (BSDC) are only word-accessible.
(3) I/O port
Ports are accessed only in bytes.
(4) Low-power Consumption Mode
Be sure to use the following sequence to enter standby mode if synchronous standby mode is being used
(the SYNCS bit (bit 8) of the TBCR (timebase counter control register) is set) :
(5) Notes on the PS register
The PS register is processed prior to the execution of some instructions, which may cause the exception
handling described below to trigger breakpoints in interrupt processing routines or to update the displayed
contents of the PS register when the debugger is being used.
In all of these situations, because the microcontroller has been designed to correctly perform reprocessing
after returning from an EIT, the operation before and after the EIT is performed according to the
specifications.
(LD1 #value_of_stanby, R0)
(LD1 #_STCR, R12)
STB R0, @R12
; Write to standby control register (STCR)
LDUB
@R12, R0
; STCR read for synchronous standby
LDUB
@R12, R0
; Dummy re-read of STCR
NOP
; NOP
× 5 for adjusted timing
NOP
The following operations are performed if, in the instruction immediately before a DIVOU or DIVOS
instruction, a user interrupt or an NMI occurs, single-step execution is performed, or break is selected
from the emulator menu.
(1)The D0 and D1 flags are updated in advance.
(2)An EIT handling routine (user interrupt, NMI, or emulator) is executed.
(3)Upon returning from the EIT, the DIVOU/DIVOS instruction is executed and the D0 and D1 flags
are updated to the same values as in (1) .
If the any of the ORCCR, STILM, MOV Ri or PS instructions is executed in order to enable interrupts
when a user interrupt source or NMI source is in the interrupt occurred state, the following operations
are performed.
(1)The PS register is updated in advance.
(2)An EIT handling routine (user interrupt and NMI) is executed.
(3)Upon returning from the EIT, the above instructions are executed and the PS register is updated
to the same value as in (1) .
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MB91316PMC-G-XXXE1 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32-bit Proprietary Microcontrollers |
| MB91319 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32-bit Microcontroller |
| MB91319R | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32-bit Proprietary Microcontrollers |
| MB91350A | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32-Bit Proprietary Microcontroller |
| MB91350A_07 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32-bit Microcontroller |
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