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參數(shù)資料
| 型號(hào)： | MB91352APMT |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | RISC MICROCONTROLLER, PQFP120 |
| 封裝： | 16 X 16 MM, 1.70 MM HEIGHT, 0.50 MM PPITCH, LEAD FREE, PLASTIC, LQFP-120 |
| 文件頁(yè)數(shù)： | 60/140頁(yè) |
| 文件大小： | 3803K |
| 代理商： | MB91352APMT |
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MB91350A Series
26
DS07-16503-5E
Prefetch
If prefetch is enabled in a area that is configured as little endian, limit access to the corresponding area to
word-length (32-bit) access.
Byte or halfword does not allow a proper access to data.
I/O Port Access
Ports can only be accessed in bytes.
Built-in RAM
Immediately after a reset is released, the internal RAM capacity restriction function begins operating, allowing
only 4 Kbytes to be used for both data and program execution irrespective of the on-chip RAM capacity.
Update the setting to clear the restriction function.
At least one NOP instruction is required immediately after updating this setting.
Please refer to the “MB91350A Series HARDWARE MANUAL CHAPTER 19 DATA INTERNAL RAM/INSTRUC-
TION INTERNAL RAM ACCESS RESTRICTION FUNCTIONS” for the details.
Flash Memory
In programming mode, Flash memory cannot be used for the interrupt vector table (However, a reset can be
performed) .
Notes on the PS Register
As the PS register is processed in advance by some instructions, when the debugger is being used, the following
exception handling may result in execution breaking in an interrupt handling routine or the displayed values of
the flags in the PS register being updated.
As the microcontroller is designed to carry out reprocessing correctly upon returning from such an EIT event,
the operation before and after the EIT always proceeds according to specification.
1. The following behavior may occur if any of the following occurs in the instruction immediately after a DIV0U/
DIV0S instruction :
(a) a user interrupt or NMI is accepted; (b) single-step execution is performed; or (c) execution breaks due
to a data event or from the emulator menu.
The D0 and D1 flags are updated in advance.
An EIT handling routine (user interrupt, NMI, or emulator) is executed.
Upon returning from the EIT, the DIV0U/DIV0S instruction is executed and the D0 and D1 flags are
updated to the same values as in (1).
2. The following behavior occurs when an ORCCR, STILM, MOV Ri or PS instruction is executed to enable a
user interrupt or NMI source while that interrupt is in the active state.
The PS register is updated in advance.
The EIT handling routine (user interrupt, NMI, or emulator) is executed.
Upon returning from the EIT, the above instructions are executed and the PS register is updated to the
same value as in (1).
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MB91353A | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32-bit Microcontroller |
| MB91353APMT | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32-bit Microcontroller |
| MB91354A | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32-bit Microcontroller |
| MB91354APMT | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32-Bit Proprietary Microcontroller |
| MB91355A | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32-bit Microcontroller |
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