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MB91350A Series
2
Register interlock functions: Facilitating coding in assemblers
On-chip multiplier supported at the instruction level.
Signed 32-bit multiplication: 5 cycles.
Signed 16-bit multiplication: 3 cycles
Interrupt (PC, PS save): 6 cycles, 16 priority levels
Harvard architecture allowing program access and data access to be executed simultaneously
FR family instruction compatible
Bus Interface
Maximum operating frequency: 25 MHz
Capable of up to 24-bit address full output (16 MB of space)
8,16-bit data output
Built-in pre-fetch buffer
Non-used data and address pin are usable as general I/O port.
Capable of chip-select signal output for completely independent four areas settable in 64 KB minimum
Support for various memory interfaces:
SRAM, ROM/Flash,
page mode Flash ROM, page mode ROM
Basic bus cycle: 2 cycles
Programmable automatic wait cycle generator capable of inserting wait cycles for each area
RDY input for external wait cycles
Support for fly-by transfer for DMA, which enables wait control of independent I/O
Mounted Memory
Memory
MB91V350A
MB91F355A
ROM
No
512 KB
RAM (stack)
16 KB
16 KB
RAM (executable)
16 KB
8 KB
2.
3.
4.
DMAC (DMA Controller)
Capable of simultaneous operation of up to 5 channels (3 channels for external
→
external operation)
Three transfer sources (external pin, internal peripheral, software) selectable by software. (Transfer can be
started from UART0/1/2.)
Addressing using 32-bit full addressing mode (increment, decrement, fixed)
Transfer modes (demand transfer, burst transfer, step transfer, block transfer)
Support for fly-by transfer (between external I/O and memory)
Selectable transfer data size: 8, 16, or 32-bit
Multi-byte transfer enabled (by software)
DMAC descriptor in IO areas (200
H
to 240
H
, 1000
H
to 1024
H
)
Bit Search Module (for REALOS)
Search for the position of the bit 1/0-changed first in 1 word from the MSB
Various Timers
4 channels of 16-bit reload timer (including 1 channel for REALOS):
Internal clock frequency selectable from among divisions by 2/8/32 (division by 64/128 selectable only for ch3)
16-bit free-running timer: 1 channel.
Output compare module: 8 channels. Input capture module: 4 channels
16-bit PPG timer 6 channels
UART
UART Full duplex double buffer 5 channel
Selectable parity On/Off
Asynchronous (start-stop synchronized) or CLK-synchronous communications selectable
5.
6.
7.
(Continued)
MB91F356B
256 KB
16 KB
8 KB
MB91355A
512 KB
16 KB
8 KB
MB91354A
384 KB
8 KB
8 KB