參數(shù)資料
型號: MB91461PMC-GSE1
元件分類: 微控制器/微處理器
英文描述: RISC MICROCONTROLLER, PQFP176
封裝: 24 X 24 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, LEAD FREE, PLASTIC, LQFP-176
文件頁數(shù): 62/84頁
文件大小: 2114K
代理商: MB91461PMC-GSE1
MB91460 Series
DS07-16602-2E
65
(4) Normal bus access read/write operation
(VCC3
= 3.0 V to 3.6 V, VSS = AVSS = 0 V, TA = 40 °C to + 85 °C)
* : When the bus timing is delayed by automatic wait insertion or RDY input, add the time (tCYC × the number of
cycles added for the delay) to this rating.
Parameter
Symbol
Pin name
Condition
Value
Unit Remarks
Min
Max
CS0 to CS4 setup
tCSLCH
SYSCLK
CS0 to CS4
3
ns
tCSDLCH
3
ns
CS0 to CS4 hold
tCHCSH
3tCYC/2
+ 6ns
Address setup
tASCH
SYSCLK
A23 to A00
3
ns
tASWL
WR0, WR1
A23 to A00
3
ns
tASRL
RD
A23 to A00
3
ns
Address hold
tCHAX
SYSCLK
A23 to A00
3tCYC/2
+ 6ns
tWHAX
WR0, WR1
A23 to A00
3
ns
tRHAX
RD
A23 to A00
3
ns
Valid address/valid data
input time
tAVDV
A23 to A00
D31 to D16
3/2
× tCYC 15 ns *
WR0, WR1 delay time
tCHWL
SYSCLK
WR0, WR1
6ns
tCHWH
6ns
Data setup time
(WRn rising)
tDSWH
D31 to D16
WR0, WR1
tCYC
3
ns
Data hold time
(WRn rising)
tWHDX
D31 to D16
WR0, WR1
3
ns
WR0, WR1 minimum pulse
width
tWLWH
WR0, WR1
tCYC
3
ns
RD delay time
tCHRL
SYSCLK
RD
6ns
tCHRH
6ns
Data setup time (RD rising)
tDSRH
D31 to D16
RD
20
ns
Data hold time (RD rising)
tRHDX
D31 to D16
RD
0
ns
RD minimum pulse width
tRLRH
RD
tCYC
3
ns
AS setup
tASLCH
SYSCLK
AS
3
ns
AS hold
tCHASH
3tCYC/2
+ 6ns
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