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參數(shù)資料
| 型號： | MB91664PMC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, MROM, 33 MHz, RISC MICROCONTROLLER, PQFP120 |
| 封裝： | 16 X 16 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LQFP-120 |
| 文件頁數(shù)： | 36/132頁 |
| 文件大?。?/td> | 4189K |
| 代理商： | MB91664PMC |
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MB91660 Series
130
DS07-16905-3E
(Continued)
Page
Section
Change Results
88, 89
■ ELECTRICAL CHARAC-
TERISTICS
4. AC Characteristics
(1) Main Clock (MCLK) Input
Standard
Corrected “
Operating guaranteed range (Not using USB)”.
(Changed from “
Operating guaranteed range” to “ Operating guaran-
teed range (Not using USB)”.)
(Changed “
When the PLL clock is selected”, and “ When the sub clock
is selected”.)
(Changed from “(Continued)” to “
Example of configuration”.)
90 to 92
Corrected “
Operating guaranteed range (at using USB)”.
(Added *1 to *4 to each value.)
(Changed from “VMS” to “PMS” for “
When the PLL clock is selected”.)
(Changed from “(Continued)” to “
Example of configuration”.)
(Added the note at the bottom of the page.)
93
(2) Sub Clock (SBCLK) Input
Standard
Added the column, “Remarks”.
Divided the line, “Input frequency” into two lines, “When crystal oscillator
is connected”, and “When using external clock”.
Corrected “Unit” for “Input clock cycle” ( ms
→ s).
Added “Input clock pulse width”, and “Input clock rise time and fall time”.
Corrected the table.
(Added “<When external clock input>”.)
(Deleted “X1” and “X1A”.)
94
(3) Conditions of PLL
Changed from “(3) PLL Oscillation Stabilization Wait Time (LOCK UP
Time)” to “(3) Conditions of PLL”.
Added the column, “Typ” below “Value”.
Added “PLL input clock frequency”, “PLL multiple rate”, and “PLL macro
oscillation clock frequency”.
(4) Regulator Voltage Stabili-
zation Wait Time
Corrected “Notes:”.
95
(5) Reset Input Standards
Added “Reset input rise time and fall time”.
Added “VIHS, tINITXF, tINITXR” to the table.
Corrected the symbol in the table.
(VIL
→ VILS)
96
(6) Clock Output Timing
Added the note to “
tCHCL : tCLCH = 1 : 1 (divided by 1, 2, 4, 6, 8)”
98
(7) External Bus Access
Read/Write Operation
Corrected the note, *.
(* : When the bus timing is delayed by an automatic wait instruction ...
→
* : When the bus timing is delayed by an automatic wait insertion ...)
102
(10) DMA Controller Timing
Corrected the symbols in the table.
(VOL
→ VILS and VOH → VIHS)
105
to
110
(12) Synchronous serial
(CSIO) timing
Changed “Notes:”.
(Deleted “
The above standards exclude 4ch synchronous communica-
tion.”.)
Corrected the symbols in the table.
(VIL
→ VILS and VIH → VIHS)
109
Corrected the table, “
Synchronous serial (SPI = 1,SCINV = 0)”.
(Corrected the length of the arrow for tSLIXE.)
110
Corrected the table, “
Synchronous serial (SPI = 1, SCINV = 1)”.
(Corrected the length of the arrow for tSHIXI.)
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