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參數(shù)資料
| 型號(hào)： | MB91F367GA |
| 廠商： | Fujitsu Limited |
| 元件分類： | 微控制器 |
| 英文描述： | 32-BIT MICROCONTROLLER |
| 中文描述： | 32位微控制器 |
| 文件頁(yè)數(shù)： | 10/62頁(yè) |
| 文件大小： | 713K |
| 代理商： | MB91F367GA |
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FME / EMDC / Br+JR - mb91f367g_f368g_ds.fm 10
10-Apr-01
1.4
Features
Function
Feature
Remarks
PPG for dimmer
(4 channels)
16-bit PWM Timer
16 bit down counter, cycle and duty set-
ting registers
interrupt at triggering, cycle or duty
match
can be triggered by software or reload
timer
PWM operation and one-shot operation
Clock disable
internal prescaler allows f
RES
/1, f
RES
/4,
f
RES
/16, f
RES
/64 as counter clock
successive approximation, internal sam-
ple and hold circuit
10-bit resolution, 5 V operation,
(conversion time: 178 cycles of CLKP)
program selectable analogue input chan-
nels:
single conversion mode
continuous conversion mode
stop conversion mode
required frequencies are 90-300 Hz
ADC
(8 channels)
interrupt at the end of a conversion can
be used to activate DMA transfer
activation by software
Prescaling is done internally
Clock disable
16-bit reload timer,
includes clock prescaler (f
RES
/2
1
, f
RES
/2
3
,
f
RES
/2
5
)
conforms to CAN specification version
2.0 A and B
automatic re-transmission in case of
error
automatic transmission responding to
remote frame
prioritized 16 message buffers for data
and IDs
supports multiple messages
flexible configuration of acceptance filter-
ing: full bit compare / full bit mask / two
partial bit masks
supports up to 1 Mb/s
Clock Disable
Basic Interval Timer
(3 channels)
CAN
(2 channels)
CAN allows TSEG2 = RSJW setting
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