參數(shù)資料
型號(hào)： MB91F465KAPMT-GSE2
廠商： FUJITSU LTD
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 80 MHz, RISC MICROCONTROLLER, PQFP120
封裝： 16 X 16 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LQFP-120
文件頁數(shù)： 59/92頁
文件大小： 2797K
代理商： MB91F465KAPMT-GSE2
MB91460K Series
62
DS07-16606-2E
(Continued)
*1 : The Interrupt Control Registers (ICRs) are located in the interrupt controller and set the interrupt level for each
interrupt request. An ICR is provided for each interrupt request.
*2 : The vector address for each EIT (exception, interrupt or trap) is calculated by adding the listed offset to the
table base register value (TBR) . The TBR specifies the top of the EIT vector table. The addresses listed in the
table are for the default TBR value (000FFC00H) . The TBR is initialized to this value by a reset. The TBR is set
to 000FFC00H after the internal boot ROM is executed.
*3 : ICR23 and ICR47 can be exchanged by setting the REALOS compatibility bit (addr 0C03H : IOS[0])
*4 : Used by REALOS
*5 : Memory Protection Unit (MPU) support
Interrupt
number
Interrupt level *1
Interrupt vector *2
DMA
Resource
number
Deci-
mal
Hexa-
decimal
Setting
Register
address
Offset
Default Vector
address
Reserved
128
80
ICR56
478H
1FCH
000FFDFCH
Reserved
129
81
1F8H
000FFDF8H
Reserved
130
82
ICR57
479H
1F4H
000FFDF4H
Reserved
131
83
1F0H
000FFDF0H
Real Time Clock
132
84
ICR58
47AH
1ECH
000FFDECH
Calibration Unit
133
85
1E8H
000FFDE8H
A/D Converter 0
134
86
ICR59
47BH
1E4H
000FFDE4H
14, 112
Reserved
135
87
1E0H
000FFDE0H
Reserved
136
88
ICR60
47CH
1DCH
000FFDDCH
Reserved
137
89
1D8H
000FFDD8H
Low Voltage Detection
138
8A
ICR61
47DH
1D4H
000FFDD4H
Reserved
139
8B
1D0H
000FFDD0H
Timebase Overflow
140
8C
ICR62
47EH
1CCH
000FFDCCH
PLL Clock Gear
141
8D
1C8H
000FFDC8H
DMA Controller
142
8E
ICR63
47FH
1C4H
000FFDC4H
Main/Sub OSC stability wait
143
8F
1C0H
000FFDC0H
Security vector
144
90
1BCH
000FFDBCH
Used by the INT instruction.
145
to
255
91
to
FF
1B8H to
000H
000FFDB8H
to
000FFC00H
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