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參數(shù)資料
| 型號(hào)： | MB91F610APMC |
| 廠商： | FUJITSU LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 33 MHz, RISC MICROCONTROLLER, PQFP120 |
| 封裝： | 16 X 16 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LQFP-120 |
| 文件頁(yè)數(shù)： | 5/53頁(yè) |
| 文件大?。?/td> | 2625K |
| 代理商： | MB91F610APMC |
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MB91460D Series
102
DS07-16612-2E
7.4.
I2C AC Timings at VDD5 = 3.0 to 5.5 V
Conditions during AC measurements
All AC tests were measured under the following conditions:
-IOdrive
= 3 mA
-VDD5
= 3.0 V to 5.5 V, Iload = 3 mA (VDD = 4.5 V to 5.5 V for MB91F467Dx)
-VSS5
= 0 V
-Ta
= 40 °C to + 105 °C
-Cl
= 50 pF
-VOL
= 0.3 × VDD5
-VOH
= 0.7 × VDD5
-EPILR
= 0, PILR = 0 (CMOS Hysteresis 0.3 × VDD5/0.7 × VDD5)
Fast mode:
(VDD5
= 3.5 V to 5.5 V, VSS5 = AVSS5 = 0 V, TA = 40 °C to + 105 °C)
*1 On MB91F467Dx only guaranteed for 4.5 V < VDD5 < 5.5 V.
*2 The noise filter will suppress single spikes with a pulse width of 0ns and between (1 to 1.5) cycles
of peripheral clock, depending on the phase relationship between I2C signals (SDA, SCL) and peripheral clock.
Note: tCLKP is the cycle time of the peripheral clock.
Parameter
Symbol
Pin name
Value
Unit
Remark
Min
Max
SCL clock frequency
fSCL
SCLn
0
400
kHz
Hold time (repeated) START
condition. After this period, the first
clock pulse is generated
tHD;STA
SCLn, SDAn
0.6
μs
LOW period of the SCL clock
tLOW
SCLn
1.3
μs
HIGH period of the SCL clock
tHIGH
SCLn
0.6
μs
Setup time for a repeated START
condition
tSU;STA
SCLn, SDAn
0.6
μs
Data hold time for I2C-bus devices
tHD;DAT
SCLn, SDAn
0
0.9
μs
Data setup time
tSU;DAT
SCLn SDAn
100
ns
Rise time of both SDA and SCL
signals
tr
SCLn, SDAn
20 + 0.1Cb
300
ns
*1
Fall time of both SDA and SCL
signals
tf
SCLn, SDAn
20 + 0.1Cb
300
ns
*1
Setup time for STOP condition
tSU;STO
SCLn, SDAn
0.6
μs
Bus free time between a STOP
and START condition
tBUF
SCLn, SDAn
1.3
μs
Capacitive load for each bus line
Cb
SCLn, SDAn
400
pF
Pulse width of spike suppressed
by input filter
tSP
SCLn, SDAn
0
(1..1.5)
×
tCLKP
ns
*2
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