參數資料
型號: MB91F669PMC
廠商: FUJITSU LTD
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 33 MHz, RISC MICROCONTROLLER, PQFP64
封裝: 10 X 10 MM, 0.50 MM, PLASTIC, LQFP-64
文件頁數: 78/104頁
文件大?。?/td> 3106K
代理商: MB91F669PMC
MB91665 Series
DS07-16916-2E
75
(7) External Bus Access Read/Write Operation
Not using USB : (VCC
AVCC 2.7 V to 3.6 V, VSS AVSS 0 V, Ta 40 C to 85 C)
Using USB : (VCC
AVCC 3.0 V to 3.6 V, VSS AVSS 0 V, Ta 40 C to 85 C)
*1 : When the bus timing is delayed by an automatic wait insertion or RDY input, add the time (tCYC
the number
of delay cycles added) to this rating.
*2 : This pin is not existed in MB91F668.
Note: When the external load capacitance C = 50 pF.
Parameter
Symbol
Pin name
Condi-
tions
Value
Unit Remarks
Min
Max
AS delay time
tCHASL
SYSCLK*2,
AS
0.6
10
ns
tCHASH
CS0 to CS3 delay time
tCHCSL
SYSCLK*2,
CS0 to CS3*2
0.6
10
ns
tCHCSH
Address delay time
tCHAV
SYSCLK*2,
A23 to A00
0.6
10
ns
tCHAX
RD delay time
tCHRL
SYSCLK*2,
RD
0.6
10
ns
tCHRH
RD minimum pulse width
tRLRH
RD
tCYC
10
ns
*1
Data setup
RD time
tDSRH
RD,
D15 to D00
18
ns
RD
data hold time
tRHDH
0
ns
WR0, WR1 delay time
tCHWL
SYSCLK*2,
WR0, WR1*2
0.6
10
ns
tCHWH
WR0, WR1 minimum pulse
width
tWLWH
WR0, WR1*2
tCYC
10
ns
*1
SYSCLK
Data output time
tCHDV
SYSCLK*2,
D15 to D00
0.6
15
ns
SYSCLK
Data hold time
tCHDX
0.6
15
ns
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