參數(shù)資料
型號: MB95F136HSPFV
廠商: FUJITSU LTD
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 10 MHz, MICROCONTROLLER, PDSO28
封裝: 8.60 X 17.75 MM, 2.80 MM HEIGHT, 1.27 MM PITCH, PLASTIC, SOP-28
文件頁數(shù): 36/55頁
文件大小: 639K
代理商: MB95F136HSPFV
MB95130H Series
41
Sampling at the falling edge of sampling clock*1 and prohibited serial clock delay*2
(ESCR register : SCES bit
= 1, ECCR register : SCDE bit = 0)
(VCC
= 5.0 V± 10%, AVSS = VSS = 0.0 V, TA = 40 °C to + 85 °C)
*1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the
serial clock.
*2 : Serial clock delay function is used to delay half clock for the output signal of serial clock.
*3 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
Parameter
Sym-
bol
Pin name
Condition
Value
Unit
Min
Max
Serial clock cycle time
tSCYC
SCK
Internal clock
operation output pin :
CL
= 80 pF + 1 TTL.
5 tMCLK*3
ns
SCK
↑→ SOT delay time
tSHOVI
SCK, SOT
95
+95
ns
Valid SIN
→ SCK↓
tIVSLI
SCK, SIN
tMCLK*3
+ 190
ns
SCK
↓→ valid SIN hold time
tSLIXI
SCK, SIN
0
ns
Serial clock “H” pulse width
tSHSL
SCK
External clock
operation output pin :
CL
= 80 pF + 1 TTL.
3 tMCLK*3
tR
ns
Serial clock “L” pulse width
tSLSH
SCK
tMCLK*3
+ 95
ns
SCK
↑→ SOT delay time
tSHOVE
SCK, SOT
2 tMCLK*3
+ 95
ns
Valid SIN
→ SCK↓
tIVSLE
SCK, SIN
190
ns
SCK
↓→ valid SIN hold time
tSLIXE
SCK, SIN
tMCLK*3
+ 95
ns
SCK fall time
tF
SCK
10
ns
SCK rise time
tR
SCK
10
ns
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