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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | MB95F136JBWPF-GE1 |
| 寤犲晢锛� | Fujitsu Semiconductor America Inc |
| 鏂囦欢闋佹暩(sh霉)锛� | 32/64闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC MCU 32KB FLASH 28SOP |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 1 |
| 绯诲垪锛� | F²MC MB95130MB |
| 鏍稿績铏曠悊鍣細 | F²MC-8FX |
| 鑺珨灏哄锛� | 8-浣� |
| 閫熷害锛� | 16MHz |
| 閫ｉ€氭€э細 | LIN锛孲IO锛孶ART/USART |
| 澶栧湇瑷�(sh猫)鍌欙細 | LVD锛孭OR锛孭WM锛學DT |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 19 |
| 绋嬪簭瀛樺劜鍣ㄥ閲忥細 | 32KB锛�32K x 8锛� |
| 绋嬪簭瀛樺劜鍣ㄩ鍨嬶細 | 闁冨瓨 |
| RAM 瀹归噺锛� | 1K x 8 |
| 闆诲 - 闆绘簮 (Vcc/Vdd)锛� | 2.4 V ~ 5.5 V |
| 鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� | A/D 8x8/10b |
| 鎸暕鍣ㄥ瀷锛� | 澶栭儴 |
| 宸ヤ綔婧害锛� | -40°C ~ 105°C |
| 灏佽/澶栨锛� | 28-SOP |
| 鍖呰锛� | 绠′欢 |
| 鍏跺畠鍚嶇ū锛� | 865-1075 |
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MB95130MB Series
38
(2) Source Clock/Machine Clock
(VCC
= 5.0 V 卤 10%, AVSS = VSS = 0.0 V, TA = 40 掳C to + 85 掳C)
*1 : Clock before setting division due to machine clock division ratio selection bit (SYCC : DIV1 and DIV0) . This
source clock is divided by the machine clock division ratio selection bit (SYCC : DIV1 and DIV0) , and it
becomes the machine clock. Further, the source clock can be selected as follows.
Main clock divided by 2
PLL multiplication of main clock (select from 1, 2, 2.5, 4 multiplication)
Sub clock divided by 2
PLL multiplication of sub clock (select from 2, 3, 4 multiplication)
*2 : Operation clock of the microcontroller. Machine clock can be selected as follows.
Source clock (no division)
Source clock divided by 4
Source clock divided by 8
Source clock divided by 16
Parameter
Symbol
Pin
name
Value
Unit
Remarks
Min
Typ
Max
Source clock
cycle time*1
(Clock before
setting division)
tSCLK
61.5
2000
ns
When using main clock
Min : FCH
= 8.125 MHz, PLL multiplied by 2
Max : FCH
= 1 MHz, divided by 2
7.6
61.0
s
When using sub clock
Min : FCL
= 32 kHz, PLL multiplied by 4
Max : FCL
= 32 kHz, divided by 2
Source clock
frequency
FSP
0.50
16.25
MHz When using main clock
FSPL
16.384
131.072
kHz When using sub clock
Machine clock
cycle time*2
(Minimum
instruction
execution time)
tMCLK
61.5
32000
ns
When using main clock
Min : FSP
= 16.25 MHz, no division
Max : FSP
= 0.5 MHz, divided by 16
7.6
976.5
s
When using sub clock
Min : FSPL
= 131 kHz, no division
Max : FSPL
= 16 kHz, divided by 16
Machine clock
frequency
FMP
0.031
16.250
MHz When using main clock
FMPL
1.024
131.072
kHz When using sub clock
FCH
(main oscillation)
FCL
(sub oscillation)
Divided by 2
Main PLL
脳 1
脳 2
脳 2.5
脳 4
Divided by 2
Sub PLL
脳 2
脳 3
脳 4
SCLK
(source clock)
Clock mode select bit
(SYCC: SCS1, SCS0)
MCLK
(machine clock)
Division
circuit
脳 1
脳 1/4
脳 1/8
脳 1/16
Outline of clock generation block
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鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| MB95F136JBWPFV | 鍒堕€犲晢:FUJITSU 鍒堕€犲晢鍏ㄧū:Fujitsu Component Limited. 鍔熻兘鎻忚堪:8-bit Microcontrollers |
| MB95F136JS | 鍒堕€犲晢:FUJITSU 鍒堕€犲晢鍏ㄧū:Fujitsu Component Limited. 鍔熻兘鎻忚堪:8-bit Proprietary Microcontrollers |
| MB95F136JSPFV-GE1 | 鍒堕€犲晢:FUJITSU 鍔熻兘鎻忚堪:8BIT MCU 32K FLASH 1K RAM SOP28 |
| MB95F136JW | 鍒堕€犲晢:FUJITSU 鍒堕€犲晢鍏ㄧū:Fujitsu Component Limited. 鍔熻兘鎻忚堪:8-bit Proprietary Microcontrollers |
| MB95F136KSPF-GE1 | 鍒堕€犲晢:FUJITSU 鍔熻兘鎻忚堪: |
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