參數(shù)資料
型號： MB95F418HPMC-G-SNE2
元件分類： 微控制器/微處理器
英文描述： MICROCONTROLLER, PQFP80
封裝： 12 X 12 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LQFP-80
文件頁數(shù)： 61/84頁
文件大小： 3886K
代理商： MB95F418HPMC-G-SNE2
MB95310L/370L Series
64
DS07-12628-2E
(Continued)
*1: R represents the pull-up resistor of the SCL0 and SDA0 lines, and C the load capacitor of the SCL0 and
SDA0 lines.
*2: See “(2) Source Clock/Machine Clock” for tMCLK.
m represents the CS4 bit and CS3 bit (bit4 and bit3) in the I2C clock control register (ICCR0).
n represents the CS2 bit to CS0 bit (bit2 to bit0) in the I2C clock control register (ICCR0).
The actual timing of I2C is determined by the values of m and n set by the machine clock (tMCLK) and the
CS4 to CS0 bits in the ICCR0 register.
Standard-mode:
m and n can be set to values in the following range: 0.9 MHz < tMCLK (machine clock) < 16.25 MHz.
The usable frequencies of the machine clock are determined by the settings of m and n as shown below.
(m, n) = (1, 8)
: 0.9 MHz < tMCLK
≤ 1 MHz
(m, n) = (1, 22), (5, 4), (6, 4), (7, 4), (8, 4)
: 0.9 MHz < tMCLK
≤ 2 MHz
(m, n) = (1, 38), (5, 8), (6, 8), (7, 8), (8, 8)
: 0.9 MHz < tMCLK
≤ 4 MHz
(m, n) = (1, 98), (5, 22), (6, 22), (7, 22)
: 0.9 MHz < tMCLK
≤ 10 MHz
(m, n) = (8, 22)
: 0.9 MHz < tMCLK
≤ 16.25 MHz
Fast-mode:
m and n can be set to values in the following range: 3.3 MHz < tMCLK (machine clock) < 16.25 MHz.
The usable frequencies of the machine clock are determined by the settings of m and n as shown below.
(m, n) = (1, 8)
: 3.3 MHz < tMCLK
≤ 4 MHz
(m, n) = (1, 22), (5, 4)
: 3.3 MHz < tMCLK
≤ 8 MHz
(m, n) = (1, 38), (6, 4), (7, 4), (8, 4)
: 3.3 MHz < tMCLK
≤ 10 MHz
(m, n) = (5, 8)
: 3.3 MHz < tMCLK
≤ 16.25 MHz
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