MB95560H/570H/580H Series
2
DS702-00010-2v0-E
(Continued)
External interrupt
Interrupt by edge detection (rising edge, falling edge, and both edges can be selected)
Can be used to wake up the device from different low power consumption (standby) modes
8/10-bit A/D converter
8-bit or 10-bit resolution can be selected.
Low power consumption (standby) modes
Stop mode
Sleep mode
Watch mode
Time-base timer mode
I/O port
MB95F562H/F563H/F564H (maximum no. of I/O ports: 16)
General-purpose I/O ports (N-ch open drain)
: 1
General-purpose I/O ports (CMOS I/O)
: 15
MB95F562K/F563K/F564K (maximum no. of I/O ports: 17)
General-purpose I/O ports (N-ch open drain)
: 2
General-purpose I/O ports (CMOS I/O)
: 15
MB95F572H/F573H/F574H (maximum no. of I/O ports: 4)
General-purpose I/O ports (N-ch open drain)
: 1
General-purpose I/O ports (CMOS I/O)
: 3
MB95F572K/F573K/F574K (maximum no. of I/O ports: 5)
General-purpose I/O ports (N-ch open drain)
: 2
General-purpose I/O ports (CMOS I/O)
: 3
MB95F582H/F583H/F584H (maximum no. of I/O ports: 12)
General-purpose I/O ports (N-ch open drain)
: 1
General-purpose I/O ports (CMOS I/O)
: 11
MB95F582K/F583K/F584K (maximum no. of I/O ports: 13)
General-purpose I/O ports (N-ch open drain)
: 2
General-purpose I/O ports (CMOS I/O)
: 11
On-chip debug
1-wire serial control
Serial writing supported (asynchronous mode)
Hardware/software watchdog timer
Built-in hardware watchdog timer
Built-in software watchdog timer
Power-on reset
A power-on reset is generated when the power is switched on.
Low-voltage detection reset circuit (available only on MB95F562K/F563K/F564K/F572K/F573K/F574K/
F582K/F583K/F584K)
Built-in low-voltage detector
Clock supervisor counter
Built-in clock supervisor counter function
Dual operation Flash memory
The program/erase operation and the read operation can be executed in different banks (upper bank/lower
bank) simultaneously.
Flash memory security function
Protects the content of the Flash memory