參數(shù)資料
型號: MB95R203AP-G-SH-JNE2
廠商: FUJITSU LTD
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 10 MHz, MICROCONTROLLER, PDIP24
封裝: 22.86 X 6.40 MM, 4.80 MM HEIGHT, 1.778 MM PITCH, PLASTIC, DIP-24
文件頁數(shù): 31/48頁
文件大小: 1990K
代理商: MB95R203AP-G-SH-JNE2
MB95R203A
DS07-12630-1E
37
(8) Low Voltage Detection
(VSS
= 0.0 V, TA = 40 °C to +85 °C)
* : LS1 and LS0 mean the LS1 bit and the LS0 bit (bit1 and bit0) for the low voltage detection interrupt control
register (LVDCR) respectively.
Parameter
Symbol
Value
Unit
Remarks
Min
Typ
Max
Low voltage
detection reset
Release voltage
VDL+
1.75
1.85
1.95
V
At power-supply rise
Detection voltage
VDL
1.65
1.75
1.85
V
At power-supply fall
Hysteresis width
VHYS
70
100
mV
FRAM power
supply monitor
Release voltage
VDL+
1.8
1.9
2.0
V
At power-supply rise
Detection voltage
VDL
1.7
1.8
1.9
V
At power-supply fall
Hysteresis width
VHYS
70
100
mV
Low voltage
detection
interrupt
Release voltage
VDL+
2.2
2.3
2.4
V
At LS1
= 0, LS0 = 0, power-sup-
ply rise*
2.4
2.5
2.6
V
At LS1
= 0, LS0 = 1, power-sup-
ply rise*
2.6
2.7
2.8
V
At LS1
= 1, LS0 = 0, power-sup-
ply rise*
2.8
2.9
3.0
V
At LS1
= 1, LS0 = 1, power-sup-
ply rise*
Detection voltage
VDL
2.1
2.2
2.3
V
At LS1
= 0, LS0 = 0, power-sup-
ply fall*
2.3
2.4
2.5
V
At LS1
= 0, LS0 = 1, power-sup-
ply fall*
2.5
2.6
2.7
V
At LS1
= 1, LS0 = 0, power-sup-
ply fall*
2.7
2.8
2.9
V
At LS1
= 1, LS0 = 1, power-sup-
ply fall*
Hysteresis width
VHYS
70
100
mV
Power-supply start voltage
Voff
1.2
V
Power-supply end voltage
Von
2.0
V
Power-supply voltage
change time
(at power supply rise)
tr
0.3
μs
Slope of power supply that
reset release signal generates
200
μs
Slope of power supply that
reset release signal generates
within rating (V1DL+, V2DL+)
Power-supply voltage
change time
(at power supply fall)
tf
0.3
μs
Slope of power supply that
reset detection signal generates
200
μs
Slope of power supply that
reset detection signal generates
within rating (V1DL, V2DL)
Reset release delay time
td1
300
μs
Reset detection delay time
td2
20
μs
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