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參數(shù)資料
| 型號： | MB95R203P-G-SH-NE2 |
| 廠商： | FUJITSU LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, 10 MHz, MICROCONTROLLER, PDIP24 |
| 封裝： | 6.40 MM X 22.86 MM, 4.80 MM HEIGHT, 1.778 MM PITCH, PLASTIC, DIP-24 |
| 文件頁數(shù)： | 30/56頁 |
| 文件大?。?/td> | 1925K |
| 代理商： | MB95R203P-G-SH-NE2 |
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MB95R203
36
DS07-12625-3E
(Vcc
= 3.3 V, Vss = 0.0 V, TA = 20 °C to +70 °C)
(Continued)
Parameter
Symbol
Pin
name
Condi-
tions
Value*2
Unit
Remarks
Min
Max
SCL clock
“L” width
tLOW
SCL
R
= 1.7 kΩ,
C
= 50 pF*1
(2
+ nm / 2) tMCLK
20
ns
Master mode
SCL clock
“H” width
tHIGH
SCL
(nm
/ 2) tMCLK
20
(nm
/ 2) tMCLK +
20
ns
Master mode
Start condition
hold time
tHD;STA
SCL
SDA
(
1 + nm / 2)
tMCLK
20
(
1 + nm / 2)
tMCLK
+ 20
ns
Master mode
maximum value is
applied when m, n
= 1, 8.
Otherwise, the min-
imum value is ap-
plid.
Stop condition
setup time
tSU;STO
SCL
SDA
(1
+ nm / 2) tMCLK
20
(1
+ nm / 2) tMCLK
+ 20
ns
Master mode
Start condition
setup time
tSU;STA
SCL
SDA
(1
+ nm / 2) tMCLK
20
(1
+ nm / 2) tMCLK
+ 20
ns
Master mode
Bus free time
between stop
condition and
start condition
tBUF
SCL
SDA
(2 nm
+ 4) tMCLK
20
ns
Data hold time
tHD;DAT
SCL
SDA
3 tMCLK
20
ns
Master mode
Data setup time
tSU;DAT
SCL
SDA
(
2 + nm / 2)
tMCLK
20
(
1 + nm / 2)
tMCLK
+ 20
ns
Master mode
When assuming
that “L” of SCL is
not extended, the
minimum value is
applied to first bit of
continuous data.
Otherwise, the
maximum value is
applied.
Setup time
between
cleaning
interrupt and
SCL rising
tSU;INT
SCL
(nm
/ 2) tMCLK
20
(1
+ nm / 2) tMCLK
+ 20
ns
Minimum value is
applied to interrupt
at 9th SCL
↓.
Maximum value is
applied to interrupt
at 8th SCL
↓.
SCL clock
“L” width
tLOW
SCL
4 tMCLK
20
ns
At reception
SCL clock
“H” width
tHIGH
SCL
4 tMCLK
20
ns
At reception
Start condition
detection
tHD;STA
SCL
SDA
4 tMCLK
20
ns
Undetected when 1
tMCLK is used at re-
ception
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