參數(shù)資料
型號: MB96F338RSAPMC-GSE2
廠商: Fujitsu Semiconductor America Inc
文件頁數(shù): 94/124頁
文件大小: 0K
描述: IC MCU FLASH 32KB RAM 144LQFP
標準包裝: 1
系列: F²MC MB96330
核心處理器: F²MC-16FX
芯體尺寸: 16-位
速度: 48MHz
連通性: CAN,EBI/EMI,I²C,LIN,SCI,UART/USART
外圍設(shè)備: DMA,LVD,LVR,POR,PWM,WDT
輸入/輸出數(shù): 124
程序存儲器容量: 544KB(544K x 8)
程序存儲器類型: 閃存
RAM 容量: 32K x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 40x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 125°C
封裝/外殼: 144-LQFP
包裝: 托盤
配用: 865-1101-ND - KIT STARTER SUPPORTS MB96330 SER
其它名稱: 865-1083
PRELIMINARY
MB96330 Series
FME-MB96330 rev 3
71
When using an opposite phase external clock, X1 (X1A) must be supplied with a clock signal which has the
opposite phase to the X0 (X0A) pins.
4.
Unused sub clock signal
If the pins X0A and X1A are not connected to an oscillator, a pull-down resistor must be connected on the X0A
pin and the X1A pin must be left open.
5.
Notes on PLL clock mode operation
If the PLL clock mode is selected and no external oscillator is operating or no external clock is supplied, the
microcontroller attempts to work with the free oscillating PLL. Performance of this operation, however, cannot
be guaranteed.
6.
Power supply pins (VCC/VSS)
It is required that all VCC-level as well as all VSS-level power supply pins are at the same potential. If there is more
than one VCC or VSS level, the device may operate incorrectly or be damaged even within the guaranteed operating
range.
VCC and VSS must be connected to the device from the power supply with lowest possible impedance.
As a measure against power supply noise, it is required to connect a bypass capacitor of about 0.1
F between
VCC and VSS as close as possible to VCC and VSS pins.
7.
Crystal oscillator and ceramic resonator circuit
Noise at X0, X1 pins or X0A, X1A pins might cause abnormal operation. It is required to provide bypass capacitors
with shortest possible distance to X0, X1 pins and X0A, X1A pins, crystal oscillator (or ceramic resonator) and
ground lines, and, to the utmost effort, that the lines of oscillation circuit do not cross the lines of other circuits.
It is highly recommended to provide a printed circuit board art work surrounding X0, X1 pins and X0A, X1A pins
with a ground area for stabilizing the operation.
It is highly recommended to evaluate the quartz/MCU or resonator/MCU system at the quartz or resonator
manufacturer, especially when using low-Q resonators at higher frequencies.
8.
Turn on sequence of power supply to A/D converter and analog inputs
It is required to turn the A/D converter power supply (AVCC, AVRH, AVRL) and analog inputs (ANn) on after
turning the digital power supply (VCC) on.
It is also required to turn the digital power off after turning the A/D converter supply and analog inputs off. In this
case, the voltage must not exceed AVRH or AVCC (turning the analog and digital power supplies simultaneously
on or off is acceptable).
9.
Pin handling when not using the A/D converter
It is required to connect the unused pins of the A/D converter as AVCC = VCC
, AVSS = AVRH = AVRL = VSS.
10. Notes on Power-on
To prevent malfunction of the internal voltage regulator, supply voltage prole while turning the power supply on
should be slower than 50
s from 0.2 V to 2.7 V.
11. Stabilization of power supply voltage
X0
X1
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