參數(shù)資料
型號(hào)： MB96F338UWAPMC-GSE2
廠商： FUJITSU LTD
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 56 MHz, MICROCONTROLLER, PQFP144
封裝： 20 X 20 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LQFP-144
文件頁數(shù)： 7/124頁
文件大小： 2581K
代理商： MB96F338UWAPMC-GSE2
MB96330 Series
104
DS07-13805-1E
I2C Timing
*1 : R,C : Pull-up resistor and load capacitor of the SCL and SDA lines.
*2 : The maximum tHDDAT have only to be met if the device does not stretch the “L” width (tLOW) of the SCL signal.
*3 : A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement
tSUDAT
≥ 250 ns must then be met.
*4 : For use at over 100 kHz, set the peripheral clock 1 to at least 6 MHz.
(TA = -40°C to 125°C, VCC = AVCC = 3.0V to 5.5V,VSS = AVSS =0V)
Parameter
Symbol
Condition
Standard-mode
Fast-mode*4
Unit
Min
Max
Min
Max
SCL clock frequency
fSCL
R
= 1.7 kΩ,
C
= 50 pF*1
0
100
0
400
kHz
Hold time (repeated) START condition
SDA
↓→SCL↓
tHDSTA
4.0
0.6
μs
“L” width of the SCL clock
tLOW
4.7
1.3
μs
“H” width of the SCL clock
tHIGH
4.0
0.6
μs
Set-up time for a repeated START condition
SCL
↑→SDA↓
tSUSTA
4.7
0.6
μs
Data hold time
SCL
↓→SDA↓↑
tHDDAT
0
3.45*2
00.9*3
μs
Data set-up time
SDA
↓↑→SCL↑
tSUDAT
250
100
ns
Set-up time for STOP condition
SCL
↑→SDA↑
tSUSTO
4.0
0.6
μs
Bus free time between a STOP and START
condition
tBUS
4.7
1.3
μs
SDA
SCL
tLOW
tSUDAT
tHDSTA
tBUS
tHDSTA
tHDDAT
tHIGH
tSUSTA
tSUSTO
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