參數(shù)資料
型號(hào): MB96F346ASAPQC-GSE2
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, 56 MHz, MICROCONTROLLER, PQFP100
封裝: 14 X 20 MM, 3.35 MM HEIGHT, 0.65 MM PITCH, PLASTIC, QFP-100
文件頁數(shù): 135/159頁
文件大小: 2625K
代理商: MB96F346ASAPQC-GSE2
Preliminary Specication
MB96300
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
77
PRELIMINARY
00038AH
DMA - Interrupt select for DMA channel 10
DISEL10
RW
00038BH
DMA - Interrupt select for DMA channel 11
DISEL11
RW
00038CH
DMA - Interrupt select for DMA channel 12
DISEL12
RW
00038DH
DMA - Interrupt select for DMA channel 13
DISEL13
RW
00038EH
DMA - Interrupt select for DMA channel 14
DISEL14
RW
00038FH
DMA - Interrupt select for DMA channel 15
DISEL15
RW
000390H
DMA status register for DMA channels 7 -
0
DSRL
DSR
RW
000391H
DMA status register for DMA channels 15
- 8
DSRH
RW
000392H
DMA stop status register for DMA
channels 7 - 0
DSSRL
DSSR
RW
000393H
DMA stop status register for DMA
channels 15 - 8
DSSRH
RW
000394H
DMA enable register for DMA channels 7 -
0
DERL
DER
RW
000395H
DMA enable register for DMA channels 15
- 8
DERH
RW
0003A0H
Interrupt level register
ILR
ICR
RW
0003A1H
Interrupt Index register
IDX
RW
0003A2H
Interrupt vector Table base register
TBRL
TBR
RW
0003A3H
Interrupt vector Table base register
TBRH
RW
0003A4H
Delayed Interrupt register
DIRR
RW
0003A5H
Non maskable Interrupt register
NMI
RW
0003AEH
ROM mirror control register
ROMM
RW
0003AFH
EDSU conguration register
EDSU
RW
0003B0H
Memory patch control/status register ch 0/
1
PFCS0
RW
0003B1H
Memory patch control/status register ch 0/
1
RW
0003B2H
Memory patch control/status register ch 2/
3
PFCS1
RW
0003B3H
Memory patch control/status register ch 2/
3
RW
Table 0-1 I/O map (15 / 53)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
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