參數(shù)資料
型號(hào): MB96F348CWBXXXPQC-GSE2
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, 56 MHz, RISC MICROCONTROLLER, PQFP100
封裝: 14 X 20 MM, 3.35 MM HEIGHT, 0.65 MM PITCH, PLASTIC, QFP-100
文件頁(yè)數(shù): 53/118頁(yè)
文件大?。?/td> 1465K
代理商: MB96F348CWBXXXPQC-GSE2
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MB96340 Series
Specication
4
FME/EMDC- 2007-9-12
MB96300_DS_features.fm
PRELIMINARY
CAN
Supports CAN protocol version 2.0 part A and B
ISO16845 certified
Bit rates up to 1 Mbit/s
32 message objects
Each message object has its own identifier mask
Programmable FIFO mode (concatenation of message objects)
Maskable interrupt
Disabled Automatic Retransmission mode for Time Triggered CAN applications
Programmable loop-back mode for self-test operation
USART
Full duplex USARTs (SCI/LIN)
Wide range of baud rate settings using a dedicated reload timer
Special synchronous options for adapting to different synchronous serial protocols
LIN functionality working either as master or slave LIN device
I2C
Up to 400 kbit/s
Master and Slave functionality, 8-bit and 10-bit addressing
A/D converter
SAR-type
10bit resolution
Signals interrupt on conversion end, single conversion mode, continuous conversion
mode, stop conversion mode, activation by software, external trigger or reload timer
A/D Converter Refer-
ence Voltage switch
2 independant positive A/D converter reference voltages available
Reload Timers
16-bit wide
Prescaler with 1/21, 1/22, 1/23, 1/24, 1/25, 1/26 of peripheral clock frequency
Event count function
Free Running Timers
Signals an interrupt on overflow, supports timer clear upon match with Output
Compare (0, 4), Prescaler with 1, 1/21, 1/22, 1/23, 1/24, 1/25, 1/26 , 1/27 ,1/28
of
peripheral clock frequency
Input Capture Units
16-bit wide
Signals an interrupt upon external event
Rising edge, falling edge or rising & falling edge sensitive
Output Compare Units
16-bit wide
Signals an interrupt when a match with 16-bit I/O Timer occurs
A pair of compare registers can be used to generate an output signal.
Feature
Description
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