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參數(shù)資料
| 型號： | MB98B7518 |
| 廠商： | Fujitsu Limited |
| 英文描述： | Dynamic Random Access Memory Card(288M動態(tài)RAM) |
| 中文描述： | 動態(tài)隨機存取記憶卡（288M動態(tài)內(nèi)存） |
| 文件頁數(shù)： | 16/26頁 |
| 文件大?。?/td> | 418K |
| 代理商： | MB98B7518 |
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16
MB98B7515/7516/7517/7518
Notes:
*1.
Voltage reference is V
SS
.
Output pin is open. Supply current depends on cycle time and output load. If V
IL
> –0.5 V, RAS = V
IL
and CAS = V
IH
, supply current depends on the number of address changes. If RAS = V
IL
and CAS
= V
IH
, the value of either I
CC1
, I
CC3
, I
CC4
or I
CC5
indicates that the address change has occurred only one
time.
A time delay of 200
μ
s (called the pause time) plus the dummy cycles (shown below) is necessary for
these elements to function after power on. The dummy cycles are one of the following: eight RAS
Only Refresh cycles, or eight CAS before RAS Refresh cycles (WE = “H”). If using the internal refresh
counter, equal to or more than eight CAS before RAS Refresh cycles must be used for the dummy
cycles.
AC characteristics must be measured by using t
T
= 5 ns.
Input reference levels for specifying the timing are the V
IH
(min.) and V
IL
(max.).The transition time (t
T
)
is the time for a output voltage to switch from V
IH
toV
IL
.
The t
RAC
(max.) is guaranteed on the condition that t
RCD
≤
t
RCD
(max.) and t
RAD
≤
t
RAD
(max.).Therefore, if
t
RCD
> t
RCD
(max.) and t
RAD
> t
RAD
(max.), t
RAC
will appear after the delay time equivalent to the difference
between t
RCD
and t
RCD
(max.) or t
RAD
and t
RAD
(max.).
If t
ASC
t
AA
- t
CAC
- (t
T
) with t
RCD
t
RCD
(max.) and t
RAD
the CAS.
If t
ASC
t
AA
- t
CAC
- (t
T
) with t
RAD
t
RAD
(max.), the access time is dependent of the column address.
2TTL + 100PF load.
The t
OFF
is defined while the internal output buffer is in high impedance.
The t
RCD
(max.) is not a critical operating point, but a max. t
RCD
value that guarantees t
RAC
(max.). In
case t
RCD
> t
RCD
(max.), the access time depends on the t
CAC
or t
AA
.
The t
RCD
(min.) = t
RAH
(min.) + 2t
T
+ t
ASC
(min.).
The t
RAD
(max.) is not a critical operating point, but a max.t
RAD
value that guarantees t
RAC
(max.). In
case t
RAD
>t
RCD
(max.), the access time depends on the t
CAC
or t
AA
.
Operation is guaranteed if one of the t
RCH
or t
RRH
is met.
If t
WCS
t
WCS
(min.), the DQ(output) pin shows open (high impedance) during this cycle.
The t
CPA
regulates the access time if the CAS releases the column address latch, and this release
consequently permits a new column address to be selected. Therefore, the t
CPA
gets longer than t
CPA
(max.) if the t
CP
is long.
Only CAS before RAS Refresh cycle is defined.
The test mode is defined.
On reading, the Bank 1 (controlled by RAS
0
and RAS
2
)and Bank 2 (controlled by RAS
1
and RAS
3
)
must not work at the same time because the DQ pin is common to both the Bank 1 and Bank 2 (the
other must be in stand-by).
*2.
*3.
*4.
*5.
*6.
*7.
t
RAD
(max.), the access time is dependent of
*8.
*9.
*10.
*11.
*12.
*13.
*14.
*15.
*16.
*17.
*18.
*19.
3. Capacity between Pins
Parameter
Symbol
Series
Min.
Max.
Units
Input Capacity (A
0
to A
9
, WE, CAS
0
to CAS
3
)
C
IN1
Common to series
—
20
pF
Input Capacity (RAS
0
to RAS
3
)
C
IN2
MB98B7515,7517
—
45
pF
MB98B7516,7518
55
pF
Input/Output Capacity (DQ
0 to
DQ
7
, DQ
9 to
DQ
16
,
DQ
18 to
DQ
25
, DQ
27 to
DQ
34
)
C
DQ1
MB98B7515,7517
—
30
pF
MB98B7516,7518
35
pF
Input/Output Capacity (DQ
8
, DQ
17
, DQ
26
, DQ
35
)
C
DQ2
MB98B7516
—
30
pF
MB98B7518
35
pF
≥
≥
≥
≤
≥
≥
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