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參數(shù)資料
| 型號： | MB98C81233 |
| 廠商： | Fujitsu Limited |
| 英文描述： | 4M-Byte5 V-Only Flash Miniature Card(單5V 電源 8M位 微型閃存卡) |
| 中文描述： | 4米Byte5 V型微型只有閃存卡（單5V的電源分位微型閃存卡） |
| 文件頁數(shù)： | 17/48頁 |
| 文件大小： | 483K |
| 代理商： | MB98C81233 |
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17
MB98C81013/81123/81233/81333-10
I
WRITE OPERATION STATUS
Hardware Sequence Flag Table
(1): Erase Suspended Sector (2): Non-Erase Suspended Sector
Notes:
*1. Performing successive read operations from the erase-suspended sector will cause D
2
, D
10
to toggle.
*2. Performing successive read operations from any address will cause D
6
, D
14
to toggle.
*3. Reading the byte address being programmed while in the erase-suspend program mode will indicate
logic ‘1’ at the D
2
, D
10
bit. However, successive reads from the erase-suspended sector will cause D
2
,
D
10
to toggle.
*4. Not applied for MB98C81013.
D7, D15 (Data# Polling)
The card features Data# Polling as a method to indicate to the host that the Program/Erase Operation are in
progress or completed. During the program operation an attempt to read the program address will produce the
compliment of the data last written to D
7
/D
15
. Upon completion of the program operation, an attempt to read the
program address will produce the true data last written to D
7
/D
15
. During the erase operation, an attempt to read
the program address will produce a “0” at the D
7
/D
15
output. Upon completion of the erase operation an attempt
to read the device will produce a “1” at the D
7
/D
15
output.
For Chip Erase, the Data# Polling is valid after the rising edge of the sixth WE# pulse in the six write pulse
sequence. For sector erase, the Data# Polling is valid after the last rising edge of the sector erase WE# pulse.
Even if the device has completed the operation and D
7
/D
15
has a valid data, the data outputs on D
0
to D
6
/D
8
to
D
14
may be still invalid. The valid data on D
0
to D
7
/D
8
to D
15
will be read on the successive read attempts.
The Data# Polling feature is only active during the programming operation, erase operation, sector erase time-
out, Erase Suspend Read mode and Erase Supend Program mode.
D6, D14 (Toggle Bit I)
The card also features the “Toggle Bit” as a method to indicate to the host system that the Program/Erase
Operation are in progress or completed.
During an Program or Erase cycle, successive attempts to read (OE# or CE# toggling) data from the card will
result in D
6
/D
14
toggling between one and zero. Once the Program or Erase cycle is completed, D
6
/D
14
will stop
toggling and valid data will be read on the next successive attempts. During programming, the Toggle Bit is valid
after the rising edge of the fourth WE# pulse in the four write pulse sequence. For chip erase, the Toggle Bit is
valid after the rising edge of the sixth WE# pulse in the six write pulse sequence. For sector erase, the Toggle
Bit is valid after the last rising edge of the sector erase WE# pulse. The Toggle Bit is also active during the sector
time out.
Either CE# or OE# toggling will cause the D
6
/D
14
to toggle.
Status
D
7
, D
15
D
6
, D
14
D
5
, D
13
D
3
, D
11
D
2
, D
10
*
4
R/B#
*
4
In
Progress
Programming
D
7
#, D
15
#
Toggle
0
0
1
0
Erasing
0
Toggle
0
1
Toggle
0
Erase Suspend
Read
(1)
1
1
0
0
Toggle *
1
1
(2)
Data
Data
Data
Data
Data
1
Erase Suspend
*
4
Program
D
7
#, D
15
#
Toggle *
2
0
0
*
1,
*
3
0
Exceeded
Time
Limits
Programming
D
7
#, D
15
#
Toggle
1
0
1
0
Erasing
0
Toggle
1
1
N/A
0
Erase Suspend
*
4
Program
D
7
#, D
15
#
Toggle
1
0
N/A
0
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