參數(shù)資料
型號： MB9AF131KPMC
廠商： FUJITSU LTD
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, RISC MICROCONTROLLER, PQFP48
封裝： 7 X 7 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, LEAD FREE, PLASTIC, LQFP-48
文件頁數(shù)： 34/80頁
文件大?。?/td> 762K
代理商： MB9AF131KPMC
4
FUJITSU SEMICONDUCTOR CONFIDENTIAL
r0.3
MB9A130L Series
DS706-00013-0v01-E
Watchdog Timer (2channels)
A watchdog timer can generate interrupts or a reset when a time-out value is reached.
This series consists of two different watchdogs, a "Hardware" watchdog and a "Software" watchdog.
"Hardware" watchdog timer is clocked by built-in low-speed CR oscillator. Therefore, "Hardware"
watchdog is active in any low power consumption mode except RTC and STOP and Deep stand-by RTC
and Deep stand-by STOP.
Clock and Reset
[Clocks]
FIve clock sources (2 external oscillators, 2 built-in CR oscillators, and Main PLL) that are dynamically
selectable.
·
Main Clock
: 4 MHz to 20MHz
·
Sub Clock
: 32.768kHz
·
Built-in high-speed CR Clock
: 4MHz
·
Built-in low-speed CR Clock
: 100kHz
·
Main PLL Clock
[Resets]
·
Reset requests from INITX pin
·
Power on reset
·
Software reset
·
Watchdog timers reset
·
Low voltage detector reset
·
Clock supervisor reset.
Clock Super Visor (CSV)
Clocks generated by built-in CR oscillators are used to supervise abnormality of the external clocks.
·
If external clock failure (clock stop) is detected, reset is asserted.
·
If external frequency anomaly is detected, interrupt or reset is asserted.
Low Voltage Detector (LVD)
This Series include 2-stage monitoring of voltage on the VCC. When the voltage falls below the voltage has
been set, Low Voltage Detector generates an interrupt or reset.
·
LVD1: error reporting via interrupt
·
LVD2: auto-reset operation
Low Power Consumption Mode
Six low power consumption modes supported.
·
SLEEP
·
TIMER
·
RTC
·
STOP
·
Deep stand-by RTC
·
Deep stand-by STOP
Debug
·
Serial Wire JTAG Debug Port (SWJ-DP)
相關(guān)PDF資料
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參數(shù)描述
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