參數(shù)資料
型號(hào): MBM29DL161BD
廠商: Fujitsu Limited
英文描述: 16M (2M x 8/1M x 16) BIT Dual Operation
中文描述: 16米(2米x 8/1M × 16)位雙操作
文件頁數(shù): 63/76頁
文件大?。?/td> 1145K
代理商: MBM29DL161BD
MBM29DL16XTD/BD
-70/90/12
63
Low V
CC
Write Inhibit
To avoid initiation of a write cycle during V
CC
power-up and power-down, a write cycle is locked out for V
CC
less
than V
LKO
(min). If V
CC
< V
LKO
, the command register is disabled and all internal program/erase circuits are
disabled. Under this condition the device will reset to the read mode. Subsequent writes will be ignored until the
V
CC
level is greater than V
LKO
. It is the users responsibility to ensure that the control pins are logically correct to
prevent unintentional writes when V
CC
is above V
LKO
(min).
If Embedded Erase Algorithm is interrupted, there is possibility that the erasing sector(s) cannot be used.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE, CE, or WE will not initiate a write cycle.
Logical Inhibit
Writing is inhibited by holding any one of OE = V
IL
, CE = V
IH
, or WE = V
IH
. To initiate a write cycle CE and WE
must be a logical zero while OE is a logical one.
Power-Up Write Inhibit
Power-up of the devices with WE = CE = V
IL
and OE = V
IH
will not accept commands on the rising edge of WE.
The internal state machine is automatically reset to the read mode on power-up.
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