參數(shù)資料
型號(hào)： MBM29DL164TE70TR
廠商： Fujitsu Limited
英文描述： 16M (2M X 8/1M X 16) BIT Dual Operation
中文描述： 16米（2米x 8/1M × 16）位雙操作
文件頁(yè)數(shù)： 20/75頁(yè)
文件大小： 1089K
代理商： MBM29DL164TE70TR
MBM29DL16XTE/BE
-70/90/12
20
I
FUNCTIONAL DESCRIPTION
Simultaneous Operation
MBM29DL16XTE/BE have feature, which is capability of reading data from one bank of memory while a program
or erase operation is in progress in the other bank of memory (simultaneous operation), in addition to the
conventional features (read, program, erase, erase-suspend read, and erase-suspend program). The bank
selection can be selected by bank address (A
15
to A
19
) with zero latency.
The MBM29DL161TE/BE have two banks which contain
Bank 1 (8KB
×
eight sectors) and Bank 2 (64KB
×
thirty-one sectors).
The MBM29DL162TE/BE have two banks which contain
Bank 1 (8KB
×
eight sectors, 64KB
×
three sectors) and Bank 2 (64KB
×
twenty eight sectors).
The MBM29DL163TE/BE have two banks which contain
Bank 1 (8KB
×
eight sectors, 64KB
×
seven sectors) and Bank 2 (64KB
×
twenty four sectors).
The MBM29DL164TE/BE have two banks which contain
Bank 1 (8KB
×
eight sectors, 64KB
×
fifteen sectors) and Bank 2 (64KB
×
sixteen sectors).
The simultaneous operation can not execute multi-function mode in the same bank. Table 10 shows combination
to be possible for simultaneous operation. (Refer to the Figure 11 Bank-to-bank Read/Write Timing Diagram.)
*: An erase operation may also be supended to read from or program to a sector not being erased.
Read Mode
The MBM29DL16XTE/BE have two control functions which must be satisfied in order to obtain data at the outputs.
CE is the power control and should be used for a device selection. OE is the output control and should be used
to gate data to the output pins if a device is selected.
Address access time (t
ACC
) is equal to the delay from stable addresses to valid output data. The chip enable
access time (t
CE
) is the delay from stable addresses and stable CE to valid data at the output pins. The output
enable access time is the delay from the falling edge of OE to valid data at the output pins. (Assuming the
addresses have been stable for at least t
ACC
-t
OE
time.) When reading out a data without changing addresses after
power-up, it is necessary to input hardware reset or to change CE pin from “H” or “L”
Table 10 Simultaneous Operation
Case
Bank 1 Status
Bank 2 Status
1
Read mode
Read mode
2
Read mode
Autoselect mode
3
Read mode
Program mode
4
Read mode
Erase mode *
5
Autoselect mode
Read mode
6
Program mode
Read mode
7
Erase mode *
Read mode
相關(guān)PDF資料
PDF描述
MBM29DL16XTD 16M (2M x 8/1M x 16) BIT Dual Operation
MBM29DL16XTE 16M (2M X 8/1M X 16) BIT Dual Operation
MBM29DL161BE70TN 16M (2M X 8/1M X 16) BIT Dual Operation
MBM29DL161BE70TR 16M (2M X 8/1M X 16) BIT Dual Operation
MBM29DL161TE70PBT 16M (2M X 8/1M X 16) BIT Dual Operation
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MBM29DL164TE-70TR 制造商:SPANSION 制造商全稱:SPANSION 功能描述:FLASH MEMORY CMOS 16M (2M X 8/1M X 16) BIT Dual Operation
MBM29DL164TE-90 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:16M (2M X 8/1M X 16) BIT Dual Operation
MBM29DL164TE-90PBT 制造商:SPANSION 制造商全稱:SPANSION 功能描述:FLASH MEMORY CMOS 16M (2M X 8/1M X 16) BIT Dual Operation
MBM29DL164TE-90TN 制造商:SPANSION 制造商全稱:SPANSION 功能描述:FLASH MEMORY CMOS 16M (2M X 8/1M X 16) BIT Dual Operation
MBM29DL164TE-90TR 制造商:SPANSION 制造商全稱:SPANSION 功能描述:FLASH MEMORY CMOS 16M (2M X 8/1M X 16) BIT Dual Operation
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