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參數(shù)資料
| 型號： | MBM29DL164TE |
| 廠商： | Fujitsu Limited |
| 英文描述： | 16M (2MX8/1MX16) BIT Dual Operation |
| 中文描述： | 1,600（2MX8/1MX16）位雙操作 |
| 文件頁數(shù)： | 39/75頁 |
| 文件大?。?/td> | 1089K |
| 代理商： | MBM29DL164TE |
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MBM29DL16XTE/BE
-70/90/12
39
The system can use DQ
6
to determine whether a sector is actively erasing or is erase-suspended. When a bank
is actively erasing (that is, the Embedded Erase Algorithm is in progress), DQ
6
toggles. When a bank enters the
Erase Suspend mode, DQ
6
stops toggling. Successive read cycles during the erase-suspend-program cause
DQ
6
to toggle.
To operate toggle bit function properly, CE or OE must be high when bank address is changed.
See Figure 10 for the Toggle Bit I timing specifications and diagrams.
DQ
5
Exceeded Timing Limits
DQ
5
will indicate if the program or erase time has exceeded the specified limits (internal pulse count). Under
these conditions DQ
5
will produce a “1”. This is a failure condition which indicates that the program or erase
cycle was not successfully completed. Data Polling is the only operating function of the devices under this
condition. The CE circuit will partially power down the device under these conditions (to approximately 2 mA).
The OE and WE pins will control the output disable functions as described in Tables 3 and 4.
The DQ
5
failure condition may also appear if a user tries to program a non blank location without erasing. In this
case the devices lock out and never complete the Embedded Algorithm operation. Hence, the system never
reads a valid data on DQ
7
bit and DQ
6
never stops toggling. Once the devices have exceeded timing limits, the
DQ
5
bit will indicate a “1.” Please note that this is not a device failure condition since the devices were incorrectly
used. If this occurs, reset the device with command sequence.
DQ
3
Sector Erase Timer
After the completion of the initial sector erase command sequence the sector erase time-out will begin. DQ
3
will
remain low until the time-out is complete. Data Polling and Toggle Bit are valid after the initial sector erase
command sequence.
If Data Polling or the Toggle Bit I indicates the device has been written with a valid erase command, DQ
3
may
be used to determine if the sector erase timer window is still open. If DQ
3
is high (“1”) the internally controlled
erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase
operation is completed as indicated by Data Polling or Toggle Bit I. If DQ
3
is low (“0”), the device will accept
additional sector erase commands. To insure the command has been accepted, the system software should
check the status of DQ
3
prior to and following each subsequent Sector Erase command. If DQ
3
were high on
the second status check, the command may not have been accepted.
See Table 13: Hardware Sequence Flags.
DQ
2
Toggle Bit II
This toggle bit II, along with DQ
6
, can be used to determine whether the devices are in the Embedded Erase
Algorithm or in Erase Suspend.
Successive reads from the erasing sector will cause DQ
2
to toggle during the Embedded Erase Algorithm. If the
devices are in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause
DQ
2
to toggle. When the devices are in the erase-suspended-program mode, successive reads from the byte
address of the non-erase suspended sector will indicate a logic “1” at the DQ
2
bit.
DQ
6
is different from DQ
2
in that DQ
6
toggles only when the standard program or Erase, or Erase Suspend
Program operation is in progress. The behavior of these two status bits, along with that of DQ
7
, is summarized
as follows:
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| MBM29DL164TE-12 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:16M (2M X 8/1M X 16) BIT Dual Operation |
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