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參數(shù)資料
| 型號： | MBM29DL321TE-90TN |
| 廠商： | Fujitsu Limited |
| 英文描述： | 32M (4M x 8/2M x 16) BIT Dual Operation |
| 中文描述： | 32M的（4米× 8/2M × 16）位雙操作 |
| 文件頁數(shù)： | 47/80頁 |
| 文件大小： | 1588K |
| 代理商： | MBM29DL321TE-90TN |
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MBM29DL32XTE/BE
-80/90/12
47
Byte/Word Configuration
The BYTE pin selects the byte (8-bit) mode or word (16-bit) mode for the MBM29DL32XTE/BE devices. When
this pin is driven high, the devices operate in the word (16-bit) mode. The data is read and programmed at DQ
0
to DQ
15
. When this pin is driven low, the devices operate in byte (8-bit) mode. Under this mode, the DQ
15
/A
-1
pin
becomes the lowest address bit and DQ
8
to DQ
14
bits are tri-stated. However, the command bus cycle is always
an 8-bit operation and hence commands are written at DQ
0
to DQ
7
and the DQ
8
to DQ
15
bits are ignored. Refer
to Figures 15, 16 and 17 for the timing diagram.
Data Protection
The MBM29DL32XTE/BE are designed to offer protection against accidental erasure or programming caused
by spurious system level signals that may exist during power transitions. During power up the devices automat-
ically reset the internal state machine in the Read mode. Also, with its control register architecture, alteration of
the memory contents only occurs after successful completion of specific multi-bus cycle command sequences.
The devices also incorporate several features to prevent inadvertent write cycles resulting form V
CC
power-up
and power-down transitions or system noise.
Low V
CC
Write Inhibit
To avoid initiation of a write cycle during V
CC
power-up and power-down, a write cycle is locked out for V
CC
less
than V
LKO
(Min.). If V
CC
< V
LKO
, the command register is disabled and all internal program/erase circuits are
disabled. Under this condition the device will reset to the read mode. Subsequent writes will be ignored until the
V
CC
level is greater than V
LKO
. It is the users responsibility to ensure that the control pins are logically correct to
prevent unintentional writes when V
CC
is above V
LKO
(Min.).
If Embedded Erase Algorithm is interrupted, there is possibility that the erasing sector(s) cannot be used.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE, CE, or WE will not initiate a write cycle.
Logical Inhibit
Writing is inhibited by holding any one of OE = V
IL
, CE = V
IH
, or WE = V
IH
. To initiate a write cycle CE and WE
must be a logical zero while OE is a logical one.
Power-Up Write Inhibit
Power-up of the devices with WE = CE = V
IL
and OE = V
IH
will not accept commands on the rising edge of WE.
The internal state machine is automatically reset to the read mode on power-up.
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| MBM29DL321TE-90TR | 32M (4M x 8/2M x 16) BIT Dual Operation |
| MBM29DL321TE12PBT | 32M (4M x 8/2M x 16) BIT Dual Operation |
| MBM29DL321TE12TN | 32M (4M x 8/2M x 16) BIT Dual Operation |
| MBM29DL321TE12TR | 32M (4M x 8/2M x 16) BIT Dual Operation |
| MBM29DL322BD-12 | 32M (4M X 8/2M X 16) BIT Dual Operation |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MBM29DL321TE90TR | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32M (4M x 8/2M x 16) BIT Dual Operation |
| MBM29DL321TE-90TR | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32M (4M x 8/2M x 16) BIT Dual Operation |
| MBM29DL322BD | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32M (4M X 8/2M X 16) BIT Dual Operation |
| MBM29DL322BD-12 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32M (4M X 8/2M X 16) BIT Dual Operation |
| MBM29DL322BD-80 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32M (4M X 8/2M X 16) BIT Dual Operation |
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