- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄377939 > MBM29DL321TE (Fujitsu Limited) 32M (4M x 8/2M x 16) BIT Dual Operation PDF資料下載
參數(shù)資料
| 型號： | MBM29DL321TE |
| 廠商： | Fujitsu Limited |
| 英文描述： | 32M (4M x 8/2M x 16) BIT Dual Operation |
| 中文描述： | 32M的（4米× 8/2M × 16）位雙操作 |
| 文件頁數(shù)： | 2/80頁 |
| 文件大小： | 1588K |
| 代理商： | MBM29DL321TE |
第1頁當(dāng)前第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁
MBM29DL32XTE/BE
-80/90/12
2
)
(Continued)
In the MBM29DL32XTE/BE, a new design concept is implemented, so called “Sliding Bank Architecture”. Under
this concept, the MBM29DL32XTE/BE can be produced a series of devices with different Bank 1/Bank 2 size
combinations; 0.5 Mb/31.5 Mb, 4 Mb/28 Mb, 8 Mb/24 Mb, 16 Mb/16 Mb.
To eliminate bus contention the devices have separate chip enable (CE), write enable (WE), and output enable
(OE) controls.
The MBM29DL32XTE/BE are pin and command set compatible with JEDEC standard E
2
PROMs. Commands
are written to the command register using standard microprocessor write timings. Register contents serve as
input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally
latch addresses and data needed for the programming and erase operations.
Typically, each sector can be programmed and verified in about 0.5 seconds.
A sector is typically erased and verified in 1.0 second. (If already completely preprogrammed.)
The devices also feature a sector erase architecture. The sector mode allows each sector to be erased and
reprogrammed without affecting other sectors. The MBM29DL32XTE/BE are erased when shipped from the
factory.
Internally generated and regulated voltages are provided for the program and erase operations. A low V
CC
detector
automatically inhibits write operations on the loss of power. The end of program or erase is detected by Data
Polling of DQ
7
, by the Toggle Bit feature on DQ
6
, or the RY/BY output pin. Once the end of a program or erase
cycle has been completed, the devices internally reset to the read mode.
The MBM29DL32XTE/BE memories electrically erase the entire chip or all bits within a sector simultaneously
via Fowler-Nordhiem tunneling. The bytes/words are programmed one byte/word at a time using the EPROM
programming mechanism of hot electron injection.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MBM29DL321TE90TR | 32M (4M x 8/2M x 16) BIT Dual Operation |
| MBM29DL322BE12TN | 32M (4M x 8/2M x 16) BIT Dual Operation |
| MBM29DL322BE12TR | 32M (4M x 8/2M x 16) BIT Dual Operation |
| MBM29DL322TD | 32M (4M X 8/2M X 16) BIT Dual Operation |
| MBM29DL322TE | 32M (4M x 8/2M x 16) BIT Dual Operation |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MBM29DL321TE12PBT | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32M (4M x 8/2M x 16) BIT Dual Operation |
| MBM29DL321TE-12PBT | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32M (4M x 8/2M x 16) BIT Dual Operation |
| MBM29DL321TE12TN | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32M (4M x 8/2M x 16) BIT Dual Operation |
| MBM29DL321TE-12TN | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32M (4M x 8/2M x 16) BIT Dual Operation |
| MBM29DL321TE12TR | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32M (4M x 8/2M x 16) BIT Dual Operation |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。