參數(shù)資料
型號(hào)： MBM29DL324BE-90TR
廠商： Fujitsu Limited
英文描述： 32M (4M x 8/2M x 16) BIT Dual Operation
中文描述： 32M的（4米× 8/2M × 16）位雙操作
文件頁數(shù)： 34/80頁
文件大小： 1588K
代理商： MBM29DL324BE-90TR
MBM29DL32XTE/BE
-80/90/12
34
I
FUNCTIONAL DESCRIPTION
Simultaneous Operation
MBM29DL32XTE/BE have feature, which is capability of reading data from one bank of memory while a program
or erase operation is in progress in the other bank of memory (simultaneous operation), in addition to the
conventional features (read, program, erase, erase-suspend read, and erase-suspend program). The bank
selection can be selected by bank address (A
15
to A
20
) with zero latency.
The MBM29DL321TE/BE have two banks which contain
Bank 1 (8KB
×
eight sectors) and Bank 2 (64KB
×
sixty-three sectors).
The MBM29DL322TE/BE have two banks which contain
Bank 1 (8KB
×
eight sectors, 64KB
×
seven sectors) and Bank 2 (64KB
×
fifty-six sectors).
The MBM29DL323TE/BE have two banks which contain
Bank 1 (8KB
×
eight sectors, 64KB
×
fifteen sectors) and Bank 2 (64KB
×
forty-eight sectors).
The MBM29DL324TE/BE have two banks which contain
Bank 1 (8KB
×
eight sectors, 64KB
×
thirty-one sectors) and Bank 2 (64KB
×
thirty-two sectors).
The simultaneous operation can not execute multi-function mode in the same bank. Table 13 shows combination
to be possible for simultaneous operation. (Refer to the Figure 11 Back-to-back Read/Write Timing Diagram.)
*: An erase operation may also be supended to read from or program to a sector not being erased.
Read Mode
The MBM29DL32XTE/BE have two control functions which must be satisfied in order to obtain data at the outputs.
CE is the power control and should be used for a device selection. OE is the output control and should be used
to gate data to the output pins if a device is selected.
Address access time (t
ACC
) is equal to the delay from stable addresses to valid output data. The chip enable
access time (t
CE
) is the delay from stable addresses and stable CE to valid data at the output pins. The output
enable access time is the delay from the falling edge of OE to valid data at the output pins. (Assuming the
addresses have been stable for at least t
ACC
-t
OE
time.) When reading out a data without changing addresses after
power-up, it is necessary to input hardware reset or to change CE pin from “H” or “L”
Table 13 Simultaneous Operation
Case
Bank 1 status
Bank 2 status
1
Read Mode
Read Mode
2
Read Mode
Autoselect Mode
3
Read Mode
Program Mode
4
Read Mode
Erase Mode *
5
Autoselect Mode
Read Mode
6
Program Mode
Read Mode
7
Erase Mode *
Read Mode
相關(guān)PDF資料
PDF描述
MBM29DL324BE12PBT 32M (4M x 8/2M x 16) BIT Dual Operation
MBM29DL324BE12TN 32M (4M x 8/2M x 16) BIT Dual Operation
MBM29DL324BE12TR 32M (4M x 8/2M x 16) BIT Dual Operation
MBM29DL324TD-12 32M (4M X 8/2M X 16) BIT Dual Operation
MBM29DL324TD-80 32M (4M X 8/2M X 16) BIT Dual Operation
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MBM29DL324TD 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32M (4M X 8/2M X 16) BIT Dual Operation
MBM29DL324TD-12 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32M (4M X 8/2M X 16) BIT Dual Operation
MBM29DL324TD-80 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32M (4M X 8/2M X 16) BIT Dual Operation
MBM29DL324TD-80PBT 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32M (4M X 8/2M X 16) BIT Dual Operation
MBM29DL324TD-80PFTN 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32M (4M X 8/2M X 16) BIT Dual Operation
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