參數(shù)資料
型號(hào): MBM29DL640E12
廠商: Fujitsu Limited
英文描述: 64 M (8 M X 8/4 M X 16) BIT Dual Operation
中文描述: 64米(8的MX 8 / 4的MX 16)位雙操作
文件頁(yè)數(shù): 37/71頁(yè)
文件大?。?/td> 913K
代理商: MBM29DL640E12
MBM29DL640E
80/90/12
37
Low V
CC
Write Inhibit
To avoid initiation of a write cycle during V
CC
power-up and power-down, a write cycle is locked out for V
CC
less
than V
LKO
(Min.) . If V
CC
<
V
LKO
, the command register is disabled and all internal program/erase circuits are
disabled. Under this condition, the device will reset to the read mode. Subsequent writes will be ignored until
the V
CC
level is greater than V
LKO
. It is the user’s responsibility to ensure that the control pins are logically correct
to prevent unintentional writes when V
CC
is above V
LKO
(Min.) .
If the Embedded Erase Algorithm is interrupted, the intervened erasing sector (s) is (are) not valid.
Write Pulse “Glitch” Protection
Noise pulses of less than 3 ns (typical) on OE, CE or WE will not initiate a write cycle.
Logical Inhibit
Writing is inhibited by holding any one of OE
=
V
IL
, CE
=
V
IH
or WE
=
V
IH
. To initiate a write cycle CE and WE
must be a logical zero while OE is a logical one.
Power-Up Write Inhibit
Power-up of the device with WE
=
CE
=
V
IL
and OE
=
V
IH
will not accept commands on the rising edge of WE.
The internal state machine is automatically reset to the read mode on power-up.
相關(guān)PDF資料
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MBM29DL640E12PBT 64 M (8 M X 8/4 M X 16) BIT Dual Operation
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MBM29DL640E12PBT 制造商:FUJITSU 制造商全稱(chēng):Fujitsu Component Limited. 功能描述:64 M (8 M X 8/4 M X 16) BIT Dual Operation
MBM29DL640E12TN 制造商:FUJITSU 制造商全稱(chēng):Fujitsu Component Limited. 功能描述:64 M (8 M X 8/4 M X 16) BIT Dual Operation
MBM29DL640E12TR 制造商:FUJITSU 制造商全稱(chēng):Fujitsu Component Limited. 功能描述:64 M (8 M X 8/4 M X 16) BIT Dual Operation
MBM29DL640E80 制造商:FUJITSU 制造商全稱(chēng):Fujitsu Component Limited. 功能描述:64 M (8 M X 8/4 M X 16) BIT Dual Operation
MBM29DL640E80PBT 制造商:FUJITSU 制造商全稱(chēng):Fujitsu Component Limited. 功能描述:64 M (8 M X 8/4 M X 16) BIT Dual Operation