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參數(shù)資料
| 型號： | MBM29DL640E12TN |
| 廠商： | FUJITSU LTD |
| 元件分類： | DRAM |
| 英文描述： | 64 M (8 M X 8/4 M X 16) BIT Dual Operation |
| 中文描述： | 4M X 16 FLASH 3V PROM, 120 ns, PDSO48 |
| 封裝： | PLASTIC, TSOP1-48 |
| 文件頁數(shù)： | 34/71頁 |
| 文件大?。?/td> | 913K |
| 代理商： | MBM29DL640E12TN |
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MBM29DL640E
80/90/12
34
DQ
7
Data Polling
The device features Data Polling as a method to indicate to the host that the Embedded Algorithms are in
progress or completed. During the Embedded Program Algorithm, an attempt to read the device will produce a
complement of data last written to DQ
7
. Upon completion of the Embedded Program Algorithm, an attempt to
read the device will produce true data last written to DQ
7
. During the Embedded Erase Algorithm, an attempt to
read the device will produce a “0” at the DQ
7
output. Upon completion of the Embedded Erase Algorithm, an
attempt to read device will produce a “1” on DQ
7
. The flowchart for Data Polling (DQ
7
) is shown in Figure 24.
For programming, the Data Polling is valid after the rising edge of the fourth write pulse in the four write pulse
sequences.
For chip erase and sector erase, the Data Polling is valid after the rising edge of the sixth write pulse in the six
write pulse sequences. Data Polling must be performed at sector addresses of sectors being erased, not pro-
tected sectors. Otherwise the status may become invalid.
If a program address falls within a protected sector, Data Polling on DQ
7
is active for approximately 1
μ
s, then
that bank returns to the read mode. After an erase command sequence is written, if all sectors selected for
erasing are protected, Data Polling on DQ
7
is active for approximately 400
μ
s, then the bank returns to read mode.
Once the Embedded Algorithm operation is close to being completed, the device data pins (DQ
7
) may change
asynchronously while the output enable (OE) is asserted low. This means that device is driving status information
on DQ
7
at one instant, and then that byte’s valid data at the next instant. Depending on when the system samples
the DQ
7
output, it may read the status or valid data. Even if device has completed the Embedded Algorithm
operation and DQ
7
has a valid data, data outputs on DQ
0
to DQ
6
may still be invalid. The valid data on DQ
0
to
DQ
7
will be read on successive read attempts.
The Data Polling feature is active only during the Embedded Programming Algorithm, Embedded Erase Algorithm
or sector erase time-out. (See Table 12.)
See Figure 9 for the Data Polling timing specifications and diagrams.
DQ
6
Toggle Bit I
The device also features the “Toggle Bit I” as a method to indicate to the host system that the Embedded
Algorithms are in progress or completed.
During Embedded Program or Erase Algorithm cycle, successive attempts to read (OE toggling) data from the
busy bank will result in DQ
6
toggling between one and zero. Once the Embedded Program or Erase Algorithm
cycle is completed, DQ
6
will stop toggling and valid data will be read on the next successive attempts. During
programming, the Toggle Bit I is valid after the rising edge of the fourth write pulse in the four write pulse
sequences. For chip erase and sector erase, the Toggle Bit I is valid after the rising edge of the sixth write pulse
in the six write pulse sequences. The Toggle Bit I is active during the sector time out.
In programming, if the sector being written is protected, the toggle bit will toggle for about 1
μ
s and then stop
toggling with data unchanged. In erase, the device will erase all selected sectors except for protected ones. If
all selected sectors are protected, the chip will toggle the toggle bit for about 400 μs and then drop back into
read mode, having data kept remained.
Either CE or OE toggling will cause DQ
6
to toggle. In addition, an Erase Suspend/Resume command will cause
DQ
6
to toggle.
The system can use DQ
6
to determine whether a sector is actively erased or is erase-suspended. When a bank
is actively erased (that is, the Embedded Erase Algorithm is in progress) , DQ
6
toggles. When a bank enters the
Erase Suspend mode, DQ
6
stops toggling. Successive read cycles during erase-suspend-program cause DQ
6
to toggle.
To operate toggle bit function properly, CE or OE must be high when bank address is changed.
See Figure 10 for the Toggle Bit I timing specifications and diagrams.
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|---|---|
| MBM29DL640E12TR | 64 M (8 M X 8/4 M X 16) BIT Dual Operation |
| MBM29DL640E80 | 64 M (8 M X 8/4 M X 16) BIT Dual Operation |
| MBM29DL640E80PBT | 64 M (8 M X 8/4 M X 16) BIT Dual Operation |
| MBM29DL640E80TN | 64 M (8 M X 8/4 M X 16) BIT Dual Operation |
| MBM29DL640E80TR | 64 M (8 M X 8/4 M X 16) BIT Dual Operation |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MBM29DL640E12TR | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:64 M (8 M X 8/4 M X 16) BIT Dual Operation |
| MBM29DL640E80 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:64 M (8 M X 8/4 M X 16) BIT Dual Operation |
| MBM29DL640E80PBT | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:64 M (8 M X 8/4 M X 16) BIT Dual Operation |
| MBM29DL640E80TN | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:64 M (8 M X 8/4 M X 16) BIT Dual Operation |
| MBM29DL640E80TR | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:64 M (8 M X 8/4 M X 16) BIT Dual Operation |
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