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參數(shù)資料
| 型號(hào)： | MBM29F002BC-55 |
| 廠商： | Fujitsu Limited |
| 英文描述： | 2M (256K X 8) BIT |
| 中文描述： | 200萬(wàn)（256K × 8）位 |
| 文件頁(yè)數(shù)： | 19/46頁(yè) |
| 文件大小： | 461K |
| 代理商： | MBM29F002BC-55 |
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19
MBM29F002TC
-55/-70/-90
/MBM29F002BC
-55/-70/-90
RESET
Hardware Reset
The MBM29F002TC/BC device may be reset by driving the RESET pin to V
IL
. The RESET pin must be kept low
(V
IL
) for at least 500 ns. Any operation in progress will be terminated and the internal state machine will be reset
to the read mode 20
μ
s after the RESET pin is driven low. If a hardware reset occurs during a program operation,
the data at that particular location will be indeterminate.
When the RESET pin is low and the internal reset is complete, the device goes to standby mode and cannot be
accessed. Also, note that all the data output pins are tri-stated for the duration of the RESET pulse. Once the
RESET pin is taken high, the device requires t
RH
of wake up time until outputs are valid for read access.
The RESET pin may be tied to the system reset input. Therefore, if a system reset occurs during the Embedded
Program or Erase Algorithm, the device will be automatically reset to read mode and this will enable the system’s
microprocessor to read the boot-up firmware from the Flash memory.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MBM29F002BC-70 | 2M (256K X 8) BIT |
| MBM29F002BC-90 | 2M (256K X 8) BIT |
| MBM29F002TC-55 | 2M (256K X 8) BIT |
| MBM29F002TC | 2M (256K X 8) BIT |
| MBM29F002TC-90 | 2M (256K X 8) BIT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MBM29F002BC-70 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:2M (256K X 8) BIT |
| MBM29F002BC-90 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:2M (256K X 8) BIT |
| MBM29F002T-90PD# | 制造商:FUJITSU 功能描述: |
| MBM29F002TC | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:2M (256K X 8) BIT |
| MBM29F002TC-55 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:2M (256K X 8) BIT |
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