15
MBM29F040C
-55/-70/-90
Write Operation Status
Notes:
1.Performing successive read operations from any address will cause DQ
6
to toggle.
2.Reading the byte address being programmed while in the erase-suspend program mode will indicate logic
“1” at the DQ
2
bit. However, successive reads from the erase-suspended sector will cause DQ
2
to toggle.
3.DQ
0
and DQ
1
are reserve pins for future use. DQ
4
is for Fujitsu internal use only.
DQ
7
Data Polling
The MBM29F040C device features Data Polling as a method to indicate to the host that the Embedded Algorithms
are in progress or completed. During the Embedded Program Algorithm an attempt to read the device will produce
the compliment of the data last written to DQ
7
. Upon completion of the Embedded Program Algorithm, an attempt
to read the device will produce the true data last written to DQ
7
. During the Embedded Erase Algorithm, an
attempt to read the device will produce a “0” at the DQ
7
output. Upon completion of the Embedded Erase Algorithm
an attempt to read the device will produce a “1” at the DQ
7
output. The flowchart for Data Polling (DQ
7
) is shown
in Figure 15.
For chip erase, and sector erase the Data Polling is valid after the rising edge of the sixth WE pulse in the six
write pulse sequence. For sector erase, the Data Polling is valid after the last rising edge of the sector erase
WE pulse. Data Polling must be performed at sector address within any of the sectors being erased and not a
protected sector. Otherwise, the status may not be valid. Once the Embedded Algorithm operation is close to
being completed, the MBM29F040C data pins (DQ
7
) may change asynchronously while the output enable (OE)
is asserted low. This means that the device is driving status information on DQ
7
at one instant of time and then
that byte’s valid data at the next instant of time. Depending on when the system samples the DQ
7
output, it may
read the status or valid data. Even if the device has completed the Embedded Algorithm operation and DQ
7
has
a valid data, the data outputs on DQ
0
to DQ
6
may be still invalid. The valid data on DQ
0
to DQ
7
will be read on
the successive read attempts.
The Data Polling feature is only active during the Embedded Programming Algorithm, Embedded Erase
Algorithm, or sector erase time-out. (See Table 6.)
See Figure 9 for the Data Polling timing specifications and diagrams.
Table 6 Hardware Sequence Flags
Status
DQ
7
DQ
6
DQ
5
DQ
3
DQ
2
In Progress
Embedded Program Algorithm
DQ
7
Toggle
0
0
1
Embedded Erase Algorithm
0
Toggle
0
1
Toggle
Erase
Suspended
Mode
Erase Suspend Read
(Erase Suspended Sector)
1
1
0
0
Toggle
Erase Suspend Read
(Non-Erase Suspended Sector)
Data
Data
Data
Data
Data
Erase Suspend Program
Non-Erase Suspended Sector)
DQ
7
Toggle
(Note 1)
0
0
1
(Note 2)
Exceeded
Time Limits
Embedded Program Algorithm
DQ
7
Toggle
1
0
1
Program/Erase in Embedded Erase Algorithm
0
Toggle
1
1
N/A
Erase
Suspended
Mode
Erase Suspend Program
(Non-Erase Suspended Sector)
DQ
7
Toggle
1
0
N/A