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參數(shù)資料
| 型號(hào)： | MBM29F040C-90PFTN |
| 廠商： | FUJITSU LTD |
| 元件分類： | DRAM |
| 英文描述： | Single-Channel Current-Limited Power Distribution Switch 5-SOT-23 -40 to 85 |
| 中文描述： | 512K X 8 FLASH 5V PROM, 90 ns, PDSO32 |
| 封裝： | PLASTIC, TSOP1-32 |
| 文件頁數(shù)： | 17/40頁 |
| 文件大?。?/td> | 424K |
| 代理商： | MBM29F040C-90PFTN |
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17
MBM29F040C
-55/-70/-90
DQ
2
Toggle Bit II
This Toggle Bit II, along with DQ
6
, can be used to determine whether the devices are in the Embedded Erase
Algorithm or in Erase Suspend.
Successive reads from the erasing sector will cause DQ
2
to toggle during the Embedded Erase Algorithm. If the
devices are in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause
DQ
2
to toggle. When the devices are in the erase-suspended-program mode, successive reads from the byte
address of the non-erase suspended sector will indicate a logic “1” at the DQ
2
bit.
DQ
6
is different from DQ
2
in that DQ
6
toggles only when the standard program or Erase, or Erase Suspend
Program operation is in progress. The behavior of these two status bits, along with that of DQ
7
, is summarized
as follows:
Notes:
1.These status flags apply when outputs are read from a sector that has been erase-suspended.
2.These status flags apply when outputs are read from the byte address of the non-erase suspended sector.
Data Protection
The MBM29F040C is designed to offer protection against accidental erasure or programming caused by spurious
system level signals that may exist during power transitions. During power up the device automatically resets
the internal state machine in the Read mode. Also, with its control register architecture, alteration of the memory
contents only occurs after successful completion of specific multi-bus cycle command sequences.
The device also incorporates several features to prevent inadvertent write cycles resulting form V
CC
power-up
and power-down transitions or system noise.
Low V
CC
Write Inhibit
To avoid initiation of a write cycle during V
CC
power-up and power-down, a write cycle is locked out for V
CC
less
than 3.2 V (typically 3.7 V). If V
CC
< V
LKO
, the command register is disabled and all internal program/erase circuits
are disabled. Under this condition the device will reset to the read mode. Subsequent writes will be ignored
until the V
CC
level is greater than V
LKO
.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE, CE, or WE will not initiate a write cycle.
Logical Inhibit
Writing is inhibited by holding any one of OE = V
IL
, CE = V
IH
, or WE = V
IH
. To initiate a write cycle CE and WE
must be a logical zero while OE is a logical one.
Mode
DQ
7
DQ
6
DQ
2
Program
DQ
7
toggles
1
Erase
0
toggles
toggles
Erase Suspend Read
(Erase-Suspended Sector)
(Note 1)
1
1
toggles
Erase Suspend Program
DQ
7
(Note 2)
toggles
1 (Note 2)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MBM29F040C-90PFTR | Single-Channel Current-Limited Power Distribution Switch 8-SOIC -40 to 85 |
| MBM29F080-12 | 8M (1M ×8) BIT Flash Memory(1M ×8 位5V 電源電壓閃速存儲(chǔ)器) |
| MBM29F080-90 | 8M (1M ×8) BIT Flash Memory(1M ×8 位5V 電源電壓閃速存儲(chǔ)器) |
| MBM29F080A-55 | 8M (1M X 8) BIT |
| MBM29F080A | Single-Channel Current-Limited Power Distribution Switch 8-MSOP-PowerPAD -40 to 85 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MBM29F040C-90PFTN-SFLE1 | 制造商:Spansion 功能描述: |
| MBM29F040C-90PFTR | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:FLASH MEMORY 4M (512K x 8) BIT |
| MBM29F080-90PFTN | 制造商:FUJITSU 功能描述: |
| MBM29F080A | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:FLASH MEMORY CMOS 8M (1M x 8) BIT |
| MBM29F080A-55 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:8M (1M X 8) BIT |
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