參數(shù)資料
型號(hào)： MBM29F160BE-90TR
廠商： FUJITSU LTD
元件分類： DRAM
英文描述： 16M (2M X 8/1M X 16) BIT
中文描述： 2M X 8 FLASH 5V PROM, 90 ns, PDSO48
封裝： PLASTIC, REVERSE, TSOP1-48
文件頁(yè)數(shù)： 20/53頁(yè)
文件大小： 251K
代理商： MBM29F160BE-90TR
MBM29F160TE
-55/-70/-90
/MBM29F160BE
-55/-70/-90
20
3. DQ
0
and DQ
1
are reserve pins for future use.
4. DQ
4
is Fujitsu internal use only.
DQ
7
Data Polling
The MBM29F160TE/BE device features Data Polling as a method to indicate to the host that the Embedded
Algorithms are in progress or completed. During the Embedded Program Algorithm, an attempt to read the
devices will produce the complement of the data last written to DQ
7
. Upon completion of the Embedded Program
Algorithm, an attempt to read the device will produce the true data last written to DQ
7
. During the Embedded
Erase Algorithm, an attempt to read the device will produce a “0” at the DQ
7
output. Upon completion of the
Embedded Erase Algorithm an attempt to read the device will produce a “1” at the DQ
7
output. The flowchart
for Data Polling (DQ
7
) is shown in Figure 21.
For chip erase and sector erase, Data Polling is valid after the rising edge of the sixth WE pulse in the six-write
pulse sequence. Data Polling must be performed at a sector address within any of the sectors being erased and
not at a protected sector. Otherwise, the status may not be valid. Once the Embedded Algorithm operation is
close to being completed, the MBM29F160TE/BE data pins (DQ
7
) may change asynchronously while the output
enable (OE) is asserted low. This means that the device is driving status information on DQ
7
at one instant of
time and then that byte’s valid data at the next instant of time. Depending on when the system samples the DQ
7
output, it may read the status or valid data. Even if the device has completed the Embedded Program Algorithm
operation and DQ
7
has a valid data, the data outputs on DQ
0
to DQ
6
may be still invalid. The valid data on DQ
0
to DQ
7
will be read on successive read attempts.
The Data Polling feature is only active during the Embedded Programming Algorithm, Embedded Erase
Algorithm or sector erase time-out.
See Figure 9 for the Data Polling timing specifications and diagrams.
DQ
6
Toggle Bit I
The MBM29F160TE/BE also feature the “Toggle Bit I” as a method to indicate to the host system that the
Embedded Algorithms are in progress or completed.
During an Embedded Program or Erase Algorithm cycle, successive attempts to read (OE toggling) data from
the device will result in DQ
6
toggling between one and zero. Once the Embedded Program or Erase Algorithm
cycle is completed, DQ
6
will stop toggling and valid data can be read on the next successive attempts. During
programming, the Toggle Bit I is valid after the rising edge of the fourth WE pulse in the four write pulse sequence.
For chip erase and sector erase, the Toggle Bit I is valid after the rising edge of the sixth WE pulse in the six-
write pulse sequence. The Toggle Bit I is active during the sector time out.
In programming, if the sector being written to is protected, the toggle bit will toggle for about 2
μ
s and then stop
toggling without the data having changed. In erase, the device will erase all the selected sectors except for the
ones that are protected. If all selected sectors are protected, the chip will toggle the Toggle Bit I for about
100
μ
s and then drop back into read mode, having changed none of the data.
Either CE or OE toggling will cause the DQ
6
to toggle. In addition, an Erase Suspend/Resume command will
cause the DQ
6
to toggle.
See Figure 10 and Figure 22 for the Toggle Bit I timing specifications and diagrams.
DQ
5
Exceeded Timing Limits
DQ
5
will indicate if the program or erase time has exceeded the specified limits (internal pulse count). Under
these conditions DQ
5
will produce a “1”. This is a failure condition which indicates that the program or erase
cycle was not successfully completed. Data Polling is the only operating function of the device under this
相關(guān)PDF資料
PDF描述
MBM29F160TE-55PFTN 16M (2M X 8/1M X 16) BIT
MBM29F160TE-55PFTR 16M (2M X 8/1M X 16) BIT
MBM29F160TE-55TN 16M (2M X 8/1M X 16) BIT
MBM29F160TE-55TR 16M (2M X 8/1M X 16) BIT
MBM29F160TE-70PFTN 16M (2M X 8/1M X 16) BIT
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MBM29F160TE 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:16M (2M X 8/1M X 16) BIT
MBM29F160TE-55 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:16M (2M X 8/1M X 16) BIT
MBM29F160TE-55PFTN 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:16M (2M X 8/1M X 16) BIT
MBM29F160TE-55PFTR 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:16M (2M X 8/1M X 16) BIT
MBM29F160TE-55TN 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:16M (2M X 8/1M X 16) BIT
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