- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄377947 > MBM29LV004BC (Fujitsu Limited) 4M (512K X 8) BIT PDF資料下載
參數(shù)資料
| 型號(hào)： | MBM29LV004BC |
| 廠商： | Fujitsu Limited |
| 英文描述： | 4M (512K X 8) BIT |
| 中文描述： | 4分（為512k × 8）位 |
| 文件頁數(shù)： | 17/52頁 |
| 文件大?。?/td> | 442K |
| 代理商： | MBM29LV004BC |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁當(dāng)前第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁
17
MBM29LV004TC
-70/-90/-12
/MBM29LV004BC
-70/-90/-12
Chip Erase
Chip erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the
“set-up” command. Two more “unlock” write cycles are then followed by the chip erase command.
Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded Erase
Algorithm command sequence the devices will automatically program and verify the entire memory for an all
zero data pattern prior to electrical erase (Preprogram function). The system is not required to provide any
controls or timings during these operations.
The automatic erase begins on the rising edge of the last write pulse in the command sequence and terminates
when the data on DQ
7
is “1” (See Write Operation Status section.) at which time the device returns to read the
mode.
Chip Erase Time; Sector Erase Time
×
All sectors + Chip Program Time (Preprogramming)
Figure 18 illustrates the Embedded Erase
TM
Algorithm using typical command strings and bus operations.
Sector Erase
Sector erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the
“set-up” command. Two more “unlock” write cycles are then followed by the Sector Erase command. The sector
address (any address location within the desired sector) is latched on the falling edge of write pulse, while the
command (Data=30H) is latched on the rising edge of write pulse. After time-out of 50
μ
s from the rising edge
of the last sector erase command, the sector erase operation will begin.
Multiple sectors may be erased concurrently by writing the six bus cycle operations on Table 6. This sequence
is followed with writes of the Sector Erase command to addresses in other sectors desired to be concurrently
erased. The time between writes must be less than 50 μs otherwise that command will not be accepted and
erasure will start. It is recommended that processor interrupts be disabled during this time to guarantee this
condition. The interrupts can be re-enabled after the last Sector Erase command is written. A time-out of 50
μ
s
from the rising edge of the last write pulse will initiate the execution of the Sector Erase command(s). If another
falling edge of the write pulse occurs within the 50
μ
s time-out window the timer is reset. (Monitor DQ
3
to determine
if the sector erase timer window is still open, see section DQ
3
, Sector Erase Timer.) Any command other than
Sector Erase or Erase Suspend during this time-out period will reset the devices to the read mode, ignoring the
previous command string. Resetting the devices once execution has begun will corrupt the data in the sector.
In that case, restart the erase on those sectors and allow them to complete. (Refer to the Write Operation Status
section for Sector Erase Timer operation.) Loading the sector erase buffer may be done in any sequence and
with any number of sectors (0 to 10).
Sector erase does not require the user to program the devices prior to erase. The devices automatically program
all memory locations in the sector(s) to be erased prior to electrical erase (Preprogram function). When erasing
a sector or sectors the remaining unselected sectors are not affected. The system is not required to provide any
controls or timings during these operations.
The automatic sector erase begins after the 50
μ
s time out from the rising edge of the write pulse pulse for the
last sector erase command pulse and terminates when the data on DQ
7
is “1” (See Write Operation Status
section.) at which time the devices return to the read mode. Data polling must be performed at an address within
any of the sectors being erased. Multiple Sector Erase Time; [Sector Erase Time + Sector Program Time
(Preprogramming)]
×
Number of Sector Erase
Figure 18 illustrates the Embedded Erase
TM
Algorithm using typical command strings and bus operations.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MBM29LV004TC | 4M (512K X 8) BIT |
| MBM29LV004TC-70PNS | 4M (512K X 8) BIT |
| MBM29LV004BC-90PNS | 4M (512K X 8) BIT |
| MBM29LV004TC-90PNS | 4M (512K X 8) BIT |
| MBM29LV004BC-70PNS | 4M (512K X 8) BIT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MBM29LV004BC-12 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:4M (512K X 8) BIT |
| MBM29LV004BC-12PNS | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:4M (512K X 8) BIT |
| MBM29LV004BC-12PTN | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:4M (512K X 8) BIT |
| MBM29LV004BC-12PTR | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:4M (512K X 8) BIT |
| MBM29LV004BC-70 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:4M (512K X 8) BIT |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。