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參數(shù)資料
| 型號： | MBM29LV004TC-12PNS |
| 廠商： | FUJITSU LTD |
| 元件分類： | DRAM |
| 英文描述： | 4M (512K X 8) BIT |
| 中文描述： | 512K X 8 FLASH 3V PROM, 120 ns, PDSO40 |
| 封裝： | PLASTIC, SON-40 |
| 文件頁數(shù)： | 24/52頁 |
| 文件大?。?/td> | 442K |
| 代理商： | MBM29LV004TC-12PNS |
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MBM29LV004TC
-70/-90/-12
/MBM29LV004BC
-70/-90/-12
24
Data Protection
The MBM29LV004TC/BC are designed to offer protection against accidental erasure or programming caused
by spurious system level signals that may exist during power transitions. During power up the devices
automatically reset the internal state machine in the Read mode. Also, with its control register architecture,
alteration of the memory contents only occurs after successful completion of specific multi-bus cycle command
sequences.
The devices also incorporate several features to prevent inadvertent write cycles resulting form V
CC
power-up
and power-down transitions or system noise.
Low V
CC
Write Inhibit
To avoid initiation of a write cycle during V
CC
power-up and power-down, a write cycle is locked out for V
CC
less
than 2.3 V (typically 2.4 V). If V
CC
< V
LKO
, the command register is disabled and all internal program/erase circuits
are disabled. Under this condition the device will reset to the read mode. Subsequent writes will be ignored until
the V
CC
level is greater than V
LKO
. It is the users responsibility to ensure that the control pins are logically correct
to prevent unintentional writes when V
CC
is above 2.3 V.
If Embedded Erase Algorithm is interrupted, there is possibility that the erasing sector(s) cannot be used.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE, CE, or WE will not initiate a write cycle.
Logical Inhibit
Writing is inhibited by holding any one of OE = V
IL
, CE = V
IH
, or WE = V
IH
. To initiate a write cycle CE and WE
must be a logical zero while OE is a logical one.
Power-Up Write Inhibit
Power-up of the devices with WE = CE = V
IL
and OE = V
IH
will not accept commands on the rising edge of write
pulse. The internal state machine is automatically reset to the read mode on power-up.
Handling of SON Package
The metal portion of marking side is connected with internal chip electrically. Please pay attention not to occur
electrical connection during operation. In worst case, it may be caused permanent damage to device or system
by excessive current.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MBM29LV004TC-12PTN | 4M (512K X 8) BIT |
| MBM29LV004TC-12PTR | 4M (512K X 8) BIT |
| MBM29LV004TC-70 | 4M (512K X 8) BIT |
| MBM29LV004TC-70PTN | 4M (512K X 8) BIT |
| MBM29LV004TC-70PTR | 4M (512K X 8) BIT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MBM29LV004TC-12PTN | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:4M (512K X 8) BIT |
| MBM29LV004TC-12PTR | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:4M (512K X 8) BIT |
| MBM29LV004TC-70 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:4M (512K X 8) BIT |
| MBM29LV004TC-70PNS | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:4M (512K X 8) BIT |
| MBM29LV004TC-70PTN | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:4M (512K X 8) BIT |
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