參數(shù)資料
型號(hào)： MBM29LV017-12PBT-SF2
廠商： FUJITSU LTD
元件分類： DRAM
英文描述： Circular Connector; No. of Contacts:41; Series:; Body Material:Aluminum; Connector Shell Size:22; Circular Contact Gender:Socket; Circular Shell Style:Jam Nut Receptacle; Insert Arrangement:22-41; MIL SPEC:MIL-C-26482 Series I RoHS Compliant: No
中文描述： 2M X 8 FLASH 3V PROM, 120 ns, PBGA48
封裝： PLASTIC, FBGA-48
文件頁(yè)數(shù)： 16/52頁(yè)
文件大?。?/td> 600K
代理商： MBM29LV017-12PBT-SF2
16
MBM29LV017
-80/-90/-12
Byte Programming
The device is programmed on a byte-by-byte basis. Programming is a four bus cycle operation. There are two
“unlock” write cycles. These are followed by the program set-up command and data write cycles. Addresses are
latched on the falling edge of CE or WE, whichever happens later and the data is latched on the rising edge of
CE or WE, whichever happens first. The rising edge of CE or WE (whichever happens first) begins programming.
Upon executing the Embedded Program Algorithm command sequence, the system is not required to provide
further controls or timings. The device will automatically provide adequate internally generated program pulses
and verify the programmed cell margin.
The automatic programming operation is completed when the data on DQ
7
is equivalent to data written to this
bit at which time the device returns to the read mode and addresses are no longer latched. (See Table 8, Hardware
Sequence Flags.) Therefore, the device requires that a valid address to the device be supplied by the system
at this particular instance of time. Hence, Data Polling must be performed at the memory location which is being
programmed.
Any commands written to the chip during this period will be ignored. If hardware reset occurs during the
programming operation, it is impossible to guarantee the data are being written.
Programming is allowed in any sequence and across sector boundaries. Beware that a data “0” cannot be
programmed back to a “1”. Attempting to do so may either hang up the device (exceed timing limits), or result
in an apparent success according to the data polling algorithm but a read from read/reset mode will show that
the data is still “0”. Only erase operations can convert “0”s to “1”s.
Figure 17 illustrates the Embedded Program
TM
Algorithm using typical command strings and bus operations.
Chip Erase
Chip erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the
“set-up” command. Two more “unlock” write cycles are then followed by the Chip Erase command.
Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded Erase
Algorithm command sequence the device will automatically program and verify the entire memory for an all zero
data pattern prior to electrical erase. The system is not required to provide any controls or timings during these
operations.
The automatic erase begins on the rising edge of the last WE pulse in the command sequence and terminates
when the data on DQ
7
is “1” (See Write Operation Status section.) at which time the device returns to read the
mode.
Figure 18 illustrates the Embedded Erase
TM
Algorithm using typical command strings and bus operations.
Sector Erase
Sector erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the
“set-up” command. Two more “unlock” write cycles are then followed by the Sector Erase command. The sector
address (any address location within the desired sector) is latched on the falling edge of WE, while the command
(Data = 30H) is latched on the rising edge of WE. After time-out of 50
μ
s from the rising edge of the last Sector
Erase command, the sector erase operation will begin.
Multiple sectors may be erased concurrently by writing the six bus cycle operations on Table 6. This sequence
is followed with writes of the Sector Erase command to addresses in other sectors desired to be concurrently
erased. The time between writes must be less than 50 μs, otherwise that command will not be accepted and
erasure will start. It is recommended that processor interrupts be disabled during this time to guarantee this
condition. The interrupts can be re-enabled after the last Sector Erase command is written. A time-out of 50
μ
s
from the rising edge of the last WE will initiate the execution of the Sector Erase command(s). If another falling
edge of the WE occurs within the 50 μs time-out window the timer is reset. (Monitor DQ
3
to determine if the
相關(guān)PDF資料
PDF描述
MBM29LV017-12PTN Circular Connector; No. of Contacts:41; Series:; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:22; Circular Contact Gender:Socket; Circular Shell Style:Jam Nut Receptacle; Insert Arrangement:22-41 RoHS Compliant: No
MBM29LV017-90PBT-SF2 RP Series - Econoline Unregulated DC-DC Converters; Input Voltage (Vdc): 15V; Output Voltage (Vdc): 24V; Power: 1W; Pot-Core Transformer - separated windings; High 5.2kVDC Isolation in compact size; Optional Continuous Short Circuit Protected; Pin Compatible with RH & RK Series; Approved for Medical Applications; UL and EN Safety Approvals; Efficiency to 82%
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MBM29LV017-12PTN 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:16M (2M X 8) BIT
MBM29LV017-12PTR 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:16M (2M X 8) BIT
MBM29LV017-80 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:16M (2M X 8) BIT
MBM29LV017-80PBT 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:16M (2M X 8) BIT
MBM29LV017-80PBT-SF2 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:16M (2M X 8) BIT
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