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參數(shù)資料
| 型號： | MBM29LV160T-90PBT-SF2 |
| 廠商： | FUJITSU LTD |
| 元件分類： | DRAM |
| 英文描述： | 16M (2M xⅴ 8/1M x 16) BIT |
| 中文描述： | 1M X 16 FLASH 3V PROM, 90 ns, PBGA48 |
| 封裝： | PLASTIC, FBGA-48 |
| 文件頁數(shù)： | 19/60頁 |
| 文件大?。?/td> | 767K |
| 代理商： | MBM29LV160T-90PBT-SF2 |
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19
MBM29LV160T
-80/-90/-12
/MBM29LV160B
-80/-90/-12
The device contains an Autoselect command operation to supplement traditional PROM programming
methodology. The operation is initiated by writing the Autoselect command sequence into the command register.
Following the last command write, a read cycle from address XX00H retrieves the manufacture code of 04H. A
read cycle from address XX01H for
×
16 (XX02H for
×
8) retrieves the device code (MBM29LV160T = C4H and
MBM29LV160B = 49H for
×
8 mode; MBM29LV160T = 22C4H and MBM29LV160B = 2249H for
×
16 mode). (See
Tables 4.1 and 4.2.)
All manufactures and device codes will exhibit odd parity with DQ
7
defined as the parity bit.
The sector state (protection or unprotection) will be indicated by address XX02H for
×
16 (XX04H for
×
8).
Scanning the sector addresses (A
19
, A
18
, A
17
, A
16
, A
15
, A
14
, A
13
, and A
12
) while (A
6
, A
1
, A
0
) = (0, 1, 0) will produce
a logical “1” at device output DQ
0
for a protected sector. The programming verification should be perform margin
mode verification on the protected sector. (See Tables 2 and 3.)
To terminate the operation, it is necessary to write the Read/Reset command sequence into the register and,
also to write the Autoselect command during the operation, by executing it after writing the Read/Reset command
sequence.
Word/Byte Programming
The device is programmed on a byte-by-byte (or word-by-word) basis. Programming is a four bus cycle operation.
There are two “unlock” write cycles. These are followed by the program set-up command and data write cycles.
Addresses are latched on the falling edge of CE or WE, whichever happens later and the data is latched on the
rising edge of CE or WE, whichever happens first. The rising edge of the last CE or WE (whichever happens
first) begins programming. Upon executing the Embedded Program Algorithm command sequence, the system
is not required to provide further controls or timings. The device will automatically provide adequate internally
generated program pulses and verify the programmed cell margin. (See Figures 6 and 7.)
The automatic programming operation is completed when the data on DQ
7
is equivalent to data written to this
bit at which time the device return to the read mode and addresses are no longer latched. (See Table 8, Hardware
Sequence Flags.) Therefore, the device requires that a valid address be supplied by the system at this time.
Hence, Data Polling must be performed at the memory location which is being programmed.
Any commands written to the chip during this period will be ignored. If hardware reset occures during the
programming operation, it is impossible to guarantee whether the data being written is correct or not.
Programming is allowed in any sequence and across sector boundaries. Beware that a data “0” cannot be
programmed back to a “1”. Attempting to do so may either hang up the device or result in an apparent success
according to the data polling algorithm but a read from read/reset mode will show that the data is still “0”. Only
erase operations can convert “0”s to “1”s.
Figure 20 illustrates the Embedded Program
TM
Algorithm using typical command strings and bus operations.
Chip Erase
Chip erase is a six-bus cycle operation. There are two “unlock” write cycles. These are followed by writing the
“set-up” command. Two more “unlock” write cycles are then followed by the chip erase command.
Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded Erase
Algorithm command sequence the device will automatically program and verify the entire memory for an all zero
data pattern prior to electrical erase. (Preprogram Function.) The system is not required to provide any controls
or timings during these operations.
The automatic erase begins on the rising edge of the last WE pulse in the command sequence and terminates
when the data on DQ
7
is “1” (See Write Operation Status section.) at which time the device returns to read mode.
(See Figure 8.)
Figure 21 illustrates the Embedded Erase
TM
Algorithm using typical command strings and bus operations.
Sector Erase
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PDF描述 |
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| MBM29LV160T-90PFTN | 16M (2M xⅴ 8/1M x 16) BIT |
| MBM29LV160T-90PN | CAP 27UF 25V ELECT FC RADIAL |
| MBM29LV160B-12 | CONNECTOR ACCESSORY |
| MBM29LV160B-12PBT | CONNECTOR ACCESSORY |
| MBM29LV160B-12PBT-SF2 | CONNECTOR ACCESSORY |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MBM29LV160T-90PCV | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:16M (2M xⅴ 8/1M x 16) BIT |
| MBM29LV160T-90PFTN | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:16M (2M xⅴ 8/1M x 16) BIT |
| MBM29LV160T-90PFTR | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:FLASH MEMORY CMOS 16M (2M x 8/1M x 16) BIT |
| MBM29LV160T-90PFTY | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:16M (2M xⅴ 8/1M x 16) BIT |
| MBM29LV160T-90PN | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:16M (2M xⅴ 8/1M x 16) BIT |
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